Principal Verification Engineer

We have an exciting opportunity in Cambridge for a Principal Verification Engineer to lead verification of open-source digital designs, including OpenTitan, RISC-V cores, OTBN, crypto accelerators, and peripherals .

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What Youll Do: Lead design, implementation, and debugging of SystemVerilog/UVM testbenches Develop verification plans, tests, and coverage strategies Mentor engineers and drive best practices Collaborate with partners to support successful tapeouts Contribute to test and CI infrastructure Requirements: 8 years in digital design verification with leadership experience Strong SystemVerilog/UVM skills Full verification lifecycle experience through tapeout xkybehq C and/or Python for test automation Git/GitHub and team collaboration experience Nice to Have: Formal verification, RISC-V/ISA experience, security verification, post-silicon debug