Bring Proficiency with tools such as Xilinx, TCL, Verilog, SystemVerilog, and UVM. Experience with FPGA architectures including Xilinx 7, Xilinx UltraScale, Intel (Altera), or Microsemi (Actel). Knowledge of high-speed interfaces such as PCIe, Ethernet, and JESD. Familiarity with auto-generated code using MATLAB/Simulink and model More ❯
requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto-generated code using model driven engineering using Matlab and Simulink More ❯
to protect personnel from threats like Improvised Explosive Devices (IEDs) in both military and civilian environments. Essential: Using FPGA technologies especially from either Xilinx, Microsemi (Actel) or Lattice and their tools Advanced verification techniques using either VHDL or System Verilog/UVM Specifying complex timing and area constraints for More ❯
Design and implement Firmware using Xilinx, TCL, Verilog, System Verilog, and UVM. Work with FPGA architectures including Xilinx 7, Xilinx UltraScale, Intel (Altera), or Microsemi (Actel). Utilise fast interfaces such as PCIe, Ethernet, and JESD. Generate auto code using Matlab and Simulink tools. Derive detailed Firmware requirements and … design tools such as Xilinx, TCL, Verilog, System Verilog, and UVM. Strong knowledge of FPGA architectures like Xilinx 7, Xilinx UltraScale, Intel (Altera), or Microsemi (Actel). Proficiency in using fast interfaces like PCIe, Ethernet, and JESD. Capability in auto-generated code using model-driven engineering tools such as More ❯
verification methodologies Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and third-party synthesis tools Ability to analyse system and/or hardware level requirements and derive detailed More ❯
