1 of 1 Permanent SystemVerilog Jobs in Bedfordshire

Senior Verification Engineer – High-Speed Networking We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols. Key Responsibilities … Python and CI/CD pipelines Collaborate with design and software teams; support bring-up using Vivado/Vitis Required Skills Strong UVM and SystemVerilog verification experience High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI Python scripting and Git-based workflows Experience with CI/CD in verification environments Familiarity ...