24 of 24 Permanent SystemVerilog Jobs in Bristol

connectivity solutions Plan verification for SoC/IP subsystems, develop test infrastructure, and perform functional verification Create test benches and test cases using Verilog, SystemVerilog, UVM, C, Formal Write embedded C code or CPU-centric tests using C Define, implement, and analyze coverage Key qualifications MSc in electrical engineering or More ❯

of own work YOU SHOULD HAVE: Over 5 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning More ❯

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field Solid understanding and hands-on experience with UVM and SystemVerilog Proficiency in scripting languages such as Perl, Python, or TCL Mid-Senior level As a Design Verification Engineer, the individual will spend their days collaborating More ❯

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field Solid understanding and hands-on experience with UVM and SystemVerilog Proficiency in scripting languages such as Perl, Python, or TCL Mid-Senior level As a Design Verification Engineer, the individual will spend their days collaborating More ❯

of verifying CPU architectures or other complex IP (e.g. GPUs, NNAs) Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Past verification ownership of a design block Analytical thinking, self-sufficiency and team collaboration skills Ability to work effectively across More ❯

of verifying CPU architectures or other complex IP (e.g. GPUs, NNAs) Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Past verification ownership of multiple design blocks Analytical thinking, self-sufficiency and strong team collaboration skills Ability to work effectively More ❯

products, including microcontrollers and connectivity SoC/IP subsystem verification planning, test infrastructure development, functional verification. Test bench and test case generation using Verilog, SystemVerilog, UVM, C, Formal. Embedded C code or writing CPU-centric tests using C. Qualifications MSc in electrical engineering or equivalent or Bachelor with industrial experience More ❯

products, including microcontrollers and connectivity SoC/IP subsystem verification planning, test infrastructure development, functional verification. Test bench and test case generation using Verilog, SystemVerilog, UVM, C, Formal. Embedded C code or writing CPU-centric tests using C. Qualifications MSc in electrical engineering or equivalent or Bachelor with industrial experience More ❯

level simulation etc ) Knowledge of verifying CPU architectures or other IP Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Analytical thinking and team collaboration skills What we'd love you to have Past verification ownership of a design block More ❯

low area, and understanding of how RTL will map to gate-level structures Familiarity with the frontend design flow Experience with hardware description languages - SystemVerilog would be desirable You must be able to relocate to Bristol or already be based in the City. Base and Bonus are on offer. Hybrid More ❯

low area, and understanding of how RTL will map to gate-level structures Familiarity with the frontend design flow Experience with hardware description languages - SystemVerilog would be desirable You must be able to relocate to Bristol or already be based in the City. Base and Bonus are on offer. Hybrid More ❯

and test plan, run regressions, reproduce, and debug functional and performance bugs. Proficiency with EDA tools (Candence, Mentor) and design languages including Verilog and systemVerilog Understanding of synthesis, static timing analysis, and netlist verifications UVM expertise Please note: You must have full UK working rights to be considered for this More ❯

and test plan, run regressions, reproduce, and debug functional and performance bugs. Proficiency with EDA tools (Candence, Mentor) and design languages including Verilog and systemVerilog Understanding of synthesis, static timing analysis, and netlist verifications UVM expertise Please note: You must have full UK working rights to be considered for this More ❯

metrics to track and report progress. Troubleshoot, debug and resolve issues while maintaining quality tracking dashboards and automated regression tests. Requirements: Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies. A solid understanding of mixed hardware/software verification approaches. Experience with RISC-V architectures More ❯

You will work closely with cross-functional teams including RF, firmware, verification, and architecture. Key Responsibilities Design and implement digital logic in Verilog/SystemVerilog for Wi-Fi MAC/PHY and related IP blocks Collaborate on micro-architecture definition and specifications Drive RTL design from concept through synthesis and … degree in Electrical Engineering, Computer Engineering, or related field 5+ years of hands-on ASIC design experience Strong RTL design skills using Verilog or SystemVerilog Experience in SoC development and integration Familiarity with Wi-Fi, wireless MAC/PHY, or DSP-based systems is a plus Good scripting skills (Python More ❯

You will work closely with cross-functional teams including RF, firmware, verification, and architecture. Key Responsibilities Design and implement digital logic in Verilog/SystemVerilog for Wi-Fi MAC/PHY and related IP blocks Collaborate on micro-architecture definition and specifications Drive RTL design from concept through synthesis and … degree in Electrical Engineering, Computer Engineering, or related field 5+ years of hands-on ASIC design experience Strong RTL design skills using Verilog or SystemVerilog Experience in SoC development and integration Familiarity with Wi-Fi, wireless MAC/PHY, or DSP-based systems is a plus Good scripting skills (Python More ❯

Firmware/FPGA Engineer Location: Multiple locations across the UK (Bristol, Bedfordshire, London, Essex) Contract Type: Inside IR35 Clearance: British Sole Passport Holder and SC Cleared or SC Clearable. Who: A leading services company specializing in Defence systems dedicated to More ❯

Firmware/FPGA Engineer Location: Multiple locations across the UK (Bristol, Bedfordshire, London, Essex) Contract Type: Inside IR35 Clearance: British Sole Passport Holder and SC Cleared or SC Clearable. Who: A leading services company specializing in Defence systems dedicated to More ❯

Job Description Firmware/FPGA Engineer Location: Multiple locations across the UK (Bristol, Bedfordshire, London, Essex) Contract Type: Inside IR35 Clearance: British Sole Passport Holder and SC Cleared or SC Clearable. Who: A leading services company specializing in Defence systems More ❯

Senior Digital Design Engineer Bristol or Oxford – 3 days onsite £75,000 - £95,000 DOE An exciting opportunity has arisen for a Senior Digital Design engineer to make the next step in their career and join an industry leading company More ❯

Senior Digital Design Engineer Bristol or Oxford – 3 days onsite £75,000 - £95,000 DOE An exciting opportunity has arisen for a Senior Digital Design engineer to make the next step in their career and join an industry leading company More ❯

Role - DV Engineer Location:EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage More ❯

investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage … concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard More ❯

Role - RTL Design/LeadLocation:EU/Remote Mandatory Skill: SoC Integrtion, IP integration RTL design & Coding RTL lint, RTL CDC Verilog/System Verilog Industry Experience : 5 to 10 years SoC Design engineer with experience working on SOCs based More ❯