16 of 16 Permanent PCIe Jobs in Cambridge

verification.Expertise in several of the following:Use of application processors, FPGAs and SoCs for data throughput and power consumption.Embedded interconnects such as DDR4, QSPI, PCIe, JESD204.ECAD tools (ideally Altium Designer) for PCB layout.C and Python on Linux (ideally embedded programming).Verilog/VHDL.DSP applied to RF.Any additional past consultancy project ...

libraries and/or memories 5D and 3D design (CoWoS, UCIe etc.) High speed, high power and/or full reticle chip design Ethernet, PCIe, LPDDR, HBM interfaces Power integrity and optimisation 2nm or 3nm technologies Chip finishing (pad rings, chip level LVS/DRC/ERC) Design for test ...

Experience of writing embedded C, ideally for Cortex M-class MCUs Good technical understanding in at least one complex IP protocol,e.g. PCIe, HDMI, USB, SDIO, AMBA bus architectures Ability to write functional coverage and SVA Good understanding of design/front-end processes Experience with low-power simulations ...

protocols (e.g. AMBA ACE-Lite/AXI/AHB/APB/CHI)Familiarity with one or more of processor subsystems, Interconnects, security subsystems, PCIe subsystems, system power management flowsKnowledge of Perl, Python or other scripting languagesAdditional InformationPlease note that a relocation package (including visa sponsorship support) is available ...

rollback protection Familiarity with Arm architecture and boot processes, including early boot stages and firmware–hardware interaction Familiarity with platform interconnects such as PCIe, and associated security considerations in device and data-center environments Experience developing automation, validation tools, or scripts, including integration into CI workflows Proficiency in C/ ...

across distributed teams. Requirements include strong electronics knowledge, embedded compute systems, high-pin-count SoCs, FPGAs/CPLDs, and expertise in high-speed interfaces (PCIe Gen5/6/7, #J-18808-Ljbffr ...

Arm is seeking an experienced RTL/architecture lead in the UK to own microarchitecture, RTL development, and high-speed interconnect integration across multiple silicon products. You translate requirements into synthesizable RTL and drive RTL ...

Senior Design Engineer Department: Hardware Employment Type: Full Time Location: Cambridge Reporting To: Tom Hollis Description We are looking for multiple Senior Design Engineers who will work on revolutionary technology that is at the leading ...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in ...

UEFI EDK II, OpenBMC or Kernel-based Virtual Machine (KVM).Knowledge of server-class SoCs, including RAS, power management, PCI Express (PCIe), Compute Express Link (CXL), memory and virtualization. In Return: Join us and help shape world-class infrastructure technology at Arm! This is your chance to grow, develop ...

collaborators and drive decisions across engineering organizations. “Nice To Have” Skills and Experience : Knowledge of server-class SoCs, including RAS, power management, PCI Express (PCIe), Compute Express Link (CXL), memory and virtualization. Familiarity with the Linux kernel, Trusted Firmware-A (TF-A), UEFI EDK II, OpenBMC or Kernel-based Virtual ...

Would you like to play a key role in defining the solution growth story in Arm Responsibilities:Participate integrating complex IP like CPU Cluster, PCIe, DDR, and other High-Speed IO IP for SoCs.Write micro-architecture specs, develop RTL, fix bugs, and run design checks.Work with the verification team … support team members to ensure project success.Assist Project Management with activities, plans, and schedules.Required Skills and Experience :Experience in crafting and incorporating subsystems for PCIe, DDR/LPDDR, HBM, UCIe, EthernetExperience in RTL design for sophisticated SoC development using Verilog and/or SystemVerilog.Proficiency in static design checks (Lint/ ...

Solutions Engineering team is looking for experienced PCIe and CXL experts in verifying the functionality and the performance of High Speed IOs at Sub-system level. New team members will join hands with other Architects, RTL design and verification engineers spread across UK, US, Canada and India to build next … knowledge of Sub-System integration verification, IO Virtualization scenario verification with Arm SMMU, Interoperability verification with Arm and Third Party IPs, performance verification, PCIe/CXL integration verification at the sub-system level. You will work with the highly skilled team to understand and review the architecture and design specifications ...

Responsibilities Own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems, including PCIe, CXL, and UALink, across multiple silicon products. Translate system and protocol requirements into implementation-ready microarchitecture specifications, interfaces, register definitions, and synthesizable RTL, ensuring detailed execution and delivery. Own the microarchitecture, RTL development, and integration … high-speed interconnect subsystems, including PCIe, CXL, and UALink, across multiple silicon products. Translate system and protocol requirements into implementation-ready microarchitecture specifications, interfaces, register definitions, and synthesizable RTL, ensuring detailed execution and delivery. Drive the development process from concept through RTL creation, subsystem integration, verification support, synthesis preparation ...

Responsibilities:Own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems, including PCIe, CXL, and UALink, across multiple silicon products. Translate system and protocol requirements into implementation-ready microarchitecture specifications, interfaces, register definitions, and synthesizable RTL, ensuring detailed execution and delivery.Drive the development process from concept through … build, microarchitecture, subsystem integration, or related semiconductor roles.Deep hands-on expertise in SystemVerilog and the development of sophisticated, high-performance digital subsystems.Deep understanding of PCIe, CXL, and UALink, covering transaction flows, ordering, flow control, retries, error handling, host/device integration, memory expansion, and coherent connectivity.Experience with coherent ...

Limited is seeking an experienced verification engineer to join a Sub-System level team focused on PCIe and CXL verification and performance analysis. You will craft test plans, build SystemVerilog/Verilog/UVM testbenches, and debug complex test failures to ensure robust IO verification. You will collaborate with ...