10 of 10 Permanent Cadence Jobs in Cambridgeshire

coding and verification. Proficiency in RTL design techniques, including synthesis, timing closure, and verification. Experience in using UVM for functional verification of ASIC designs. Experience with EDA tools like Cadence and Synopsys for design simulation and verification. Extensive experience with FPGA emulation, design tools, and verification. Contact: For further information please contact Mícheál at Software Placements on More ❯

with cross-functional teams to enable system bring-up, debug, and feature validation on emulation platforms. Support compilation, deployment, and debug flows for emulation systems such as Synopsys ZeBu, Cadence Palladium, and Siemens Strato. Solve simulation/emulation mismatches and system-level test failures. Work closely with EDA vendors to deploy new capabilities, resolve tool issues, and influence future More ❯

and specify architectural features Expert-level Verilog/SystemVerilog for design and verification Familiarity with scripting languages (Bash, Python, Tcl, etc) The following would also be useful: Experience of Cadence simulation tool flow Experience with ASIC/FPGA synthesis and implementation, embedded systems, DFT architecture and insertion, software development, scripting More ❯

methodologies to improve GPU power, performance and area (PPA). Required Skills and Experience : Experience with hardware description languages (System Verilog preferable). Experience using EDA simulators (Siemens, Synopsys, Cadence) Strong problem solving and debugging skills, and ability to closely collaborate with other teams. Experience working with version control and code review systems such as Git and Gerrit Proficiency More ❯

across a portfolio of design tools. This role offers an exciting opportunity to work at the intersection of computational software and artificial intelligence, helping to shape the future of Cadence's innovative solutions. Responsibilities: Contribute to the development of AI infrastructure that supports inference, prompt engineering, fine-tuning, and model quantization. Assist in developing software systems and libraries to More ❯

cross-functional communication skills. Desirable Skills and Experience Knowledge of fabless product development cycles and foundry interactions. Previous experience using electronics test and semiconductor prober equipment. Previous experience with Cadence IC Design tools or similar. Previous experience in a technical lead role, actively leading projects to successful outcomes. Pragmatic Semiconductor is committed to equity, equality, diversity, and inclusion; we More ❯

for driving cross-functional execution, resolving roadblocks, and keeping our delivery milestones on track. The engineering team is functionally managed by disciplined leads, while you own project planning, execution cadence, and alignment with our business goals. Reporting Line: This role will initially report to the CEO. However, as Forefront RF grows and evolves its senior leadership, a Chief Operating More ❯

validation Technical documentation What We're Looking For: Prior industry experience in mixed signal IC design Solid background in CMOS technology and processes Experience with EDA tools such as Cadence and SPICE Strong communication and problem-solving skills Low-power design experience If you're interested in making an application to the Mixed Signal Design Engineer opportunity or would More ❯

and external teams, facilitating communication between IC and module design functions. Bachelor's or master's degree in electrical engineering, microelectronics, or something similar. Extensive hands-on experience with Cadence design tools; familiarity with ADS Momentum/RF Pro and Mentor Graphics DRC/LVA/PEX is a plus. Deep expertise in RF IC design using various silicon More ❯

Methodology) and coverage-driven verification Skilled in analyzing waveforms, simulation outputs, and debugging complex digital behaviors Synthesis, Implementation & File Generation Proficient in synthesis and implementation using: Synopsys Design Compiler Cadence Genus Xilinx Vivado Intel Quartus Prime Experienced in generating and managing key implementation deliverables: .lib files for timing and cell characterization .lef files for physical abstraction of standard cells … Pattern Generation (ATPG) and analyzing test coverage reports Understanding of DFT constraints and impact on design timing and area Tools & Workflow Automation Experienced with industry-standard EDA tools : Synopsys, Cadence, Siemens/Mentor, Xilinx, Intel Proficient in version control systems such as Git for collaborative development Skilled in scripting and workflow automation using Python , TCL , Make , and Shell scripting More ❯