SENIOR PRINCIPAL SOC IP DESIGN VERIFICATION ENGINEER - CAMBRIDGE- ENG
Cambridge, Cambridgeshire, United Kingdom
Software Placements
coding and verification. Proficiency in RTL design techniques, including synthesis, timing closure, and verification. Experience in using UVM for functional verification of ASIC designs. Experience with EDA tools like Cadence and Synopsys for design simulation and verification. Extensive experience with FPGA emulation, design tools, and verification. Contact: For further information please contact Mícheál at Software Placements on More ❯
Employment Type: Permanent
Salary: GBP Annual
Posted: