6 of 6 Permanent Synopsys Jobs in Cambridgeshire

pattern development, scan compression, Memory BIST, Logic BIST, JTAG, IJTAG, fault simulation, debug, verification, SSN, designing and conducting experiments/tool evaluations. Experience with Siemens, Cadence and/or Synopsys DFT tools Qualified candidates will have a university degree (or equivalent) in Electronic Engineering, Computer Engineering, or other relevant technical subject area. "Nice To Have" Skills and Experience : Familiarity with More ❯

verification. Proficiency in RTL design techniques, including synthesis, timing closure, and verification. Experience in using UVM for functional verification of ASIC designs. Experience with EDA tools like Cadence and Synopsys for design simulation and verification. Extensive experience with FPGA emulation, design tools, and verification. Contact: For further information please contact Mícheál at Software Placements on 00353 1 or email More ❯

SoCs. Partner with cross-functional teams to enable system bring-up, debug, and feature validation on emulation platforms. Support compilation, deployment, and debug flows for emulation systems such as Synopsys ZeBu, Cadence Palladium, and Siemens Strato. Solve simulation/emulation mismatches and system-level test failures. Work closely with EDA vendors to deploy new capabilities, resolve tool issues, and influence More ❯

and methodologies to improve GPU power, performance and area (PPA). Required Skills and Experience : Experience with hardware description languages (System Verilog preferable). Experience using EDA simulators (Siemens, Synopsys, Cadence) Strong problem solving and debugging skills, and ability to closely collaborate with other teams. Experience working with version control and code review systems such as Git and Gerrit Proficiency More ❯

tools desired. Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, Cell Aware etc. Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other state of the art EDA tools. Experience in MBIST implementation and verification will be a strong plus. Good understanding of STA concepts having handled DFT … timing closure before would be a plus. Experience in Spyglass based DFT DRC checks at RTL level would be a plus. Experience with Synopsys Design Compiler/Test Compiler/Fusion Compiler etc would be a plus. Prior experience in working with Version control systems like perforce, git etc would be critical. Understanding of Logic Equivalence, CDC, Lint, UPF/ More ❯

how often (in days) to receive an alert: Date: Jul 7, 2025 Location: Cambridge, GB, CB1 7EG Company: Ansys Requisition #: 16326 Ansys is now a part of Synopsys. Synopsys, Inc. (Nasdaq: SNPS) accelerates technology innovation from silicon to systems. Catalyzing the era of pervasive intelligence, we deliver design solutions, from electronic design automation to silicon IP, to system design … total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Ansys, part of Synopsys, we want talented people of every background to feel valued and supported to do their best work. We consider all applicants for employment without regard to race, color, religion, national … origin, gender, sexual orientation, age, military veteran status, or disability. Stay safe from recruitment fraud! We are aware of scams targeting Ansys, part of Synopsys and other companies that involve individuals posing as employees to illegitimately conduct interviews and extend false employment offers and payments to gain access to candidates' sensitive personal and financial information. All Ansys job applicants are More ❯