Test Engineer
cambridge, east anglia, united kingdom
IC Resources
flows. Hands-on expertise in scan stitching, ATPG, boundary scan, on-chip clocking , and DFT partitioning . Proficient in using modern DFT tools (e.g., Synopsys, Cadence, or Mentor platforms). Solid understanding of RTL design , STA , and silicon test methodologies . A proactive, solution-oriented mindset and excellent collaboration skills. More ❯
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