A cutting-edge startup in Cambridge is seeking a visionary Head of FPGA to lead the design and development of ultra-lowlatency trading infrastructure. This is a unique opportunity to drive hardware strategy and oversee a talented engineering team at the forefront of technological innovation. Your work … hardware engineering roadmap, with a sharp focus on ASIC design and high-performance FPGA solutions. Drive Design Excellence: Architect and oversee the development of low-latency, high-speed hardware systems that power next-generation trading platforms. Foster Collaboration: Work closely with software teams, system architects, and business stakeholders … be key to driving the team forward. You should have: Extensive FPGA Development Experience – Proficiency in VHDL/Verilog, with a strong understanding of low-latency optimisation. ASIC Design Mastery – A track record of delivering ASIC projects that meet demanding performance metrics. Strategic Vision and Leadership – Ability to More ❯
A cutting-edge startup in Cambridge is seeking a visionary Head of FPGA to lead the design and development of ultra-lowlatency trading infrastructure. This is a unique opportunity to drive hardware strategy and oversee a talented engineering team at the forefront of technological innovation. Your work … hardware engineering roadmap, with a sharp focus on ASIC design and high-performance FPGA solutions. Drive Design Excellence: Architect and oversee the development of low-latency, high-speed hardware systems that power next-generation trading platforms. Foster Collaboration: Work closely with software teams, system architects, and business stakeholders … be key to driving the team forward. You should have: Extensive FPGA Development Experience - Proficiency in VHDL/Verilog, with a strong understanding of low-latency optimisation. ASIC Design Mastery - A track record of delivering ASIC projects that meet demanding performance metrics. Strategic Vision and Leadership - Ability to More ❯
A cutting-edge startup in Cambridge is seeking a visionary Head of FPGA to lead the design and development of ultra-lowlatency trading infrastructure. This is a unique opportunity to drive hardware strategy and oversee a talented engineering team at the forefront of technological innovation. Your work … hardware engineering roadmap, with a sharp focus on ASIC design and high-performance FPGA solutions. Drive Design Excellence: Architect and oversee the development of low-latency, high-speed hardware systems that power next-generation trading platforms. Foster Collaboration: Work closely with software teams, system architects, and business stakeholders … be key to driving the team forward. You should have: Extensive FPGA Development Experience – Proficiency in VHDL/Verilog, with a strong understanding of low-latency optimisation. ASIC Design Mastery – A track record of delivering ASIC projects that meet demanding performance metrics. Strategic Vision and Leadership – Ability to More ❯
A cutting-edge startup in Cambridge is seeking a visionary Head of FPGA to lead the design and development of ultra-lowlatency trading infrastructure. This is a unique opportunity to drive hardware strategy and oversee a talented engineering team at the forefront of technological innovation. Your work … hardware engineering roadmap, with a sharp focus on ASIC design and high-performance FPGA solutions. Drive Design Excellence: Architect and oversee the development of low-latency, high-speed hardware systems that power next-generation trading platforms. Foster Collaboration: Work closely with software teams, system architects, and business stakeholders … be key to driving the team forward. You should have: Extensive FPGA Development Experience – Proficiency in VHDL/Verilog, with a strong understanding of low-latency optimisation. ASIC Design Mastery – A track record of delivering ASIC projects that meet demanding performance metrics. Strategic Vision and Leadership – Ability to More ❯
computing skills. You will learn quantum computing along the way. As Senior Digital Design Engineer at Riverlane, you will help develop a multi-FPGA, low-latency, high throughput system that needs to perform complex operations, in a predictable and guaranteed way.You will use your knowledge and expertise to … a Senior Digital Design Engineer at Riverlane, you will work on one of these key areas: Implementation of QEC decoders on hardware; Implementation of low-latency, high throughput data movement between cards and IPs; or Design of low-latency interfaces to bring data in the systems. More ❯
reward employees with a range of bonus incentives and employee benefits. The Role The successful candidate will assist with the development and maintenance of lowlatency trading platforms in an agile environment, working in the full development life cycle of applications using C/C++. We’re looking … Agile working, TDD/BDD, CI/CD. Typical Job duties would include: Develop and implement applications written in C/C++ supporting our lowlatency trading platform. Work across the full development life cycle to create new features while maintaining and testing existing applications. Support our clients More ❯
reward employees with a range of bonus incentives and employee benefits. The Role The successful candidate will assist with the development and maintenance of lowlatency trading platforms in an agile environment, working in the full development life cycle of applications using C/C++. We’re looking … Agile working, TDD/BDD, CI/CD. Typical Job duties would include: Develop and implement applications written in C/C++ supporting our lowlatency trading platform. Work across the full development life cycle to create new features while maintaining and testing existing applications. Support our clients More ❯
reward employees with a range of bonus incentives and employee benefits. The Role The successful candidate will assist with the development and maintenance of lowlatency trading platforms in an agile environment, working in the full development life cycle of applications using C/C++. We’re looking … Agile working, TDD/BDD, CI/CD. Typical Job duties would include: Develop and implement applications written in C/C++ supporting our lowlatency trading platform. Work across the full development life cycle to create new features while maintaining and testing existing applications. Support our clients More ❯
reward employees with a range of bonus incentives and employee benefits. The Role The successful candidate will assist with the development and maintenance of lowlatency trading platforms in an agile environment, working in the full development life cycle of applications using C/C++. We’re looking … Agile working, TDD/BDD, CI/CD. Typical Job duties would include: Develop and implement applications written in C/C++ supporting our lowlatency trading platform. Work across the full development life cycle to create new features while maintaining and testing existing applications. Support our clients More ❯
A cutting-edge startup in Cambridge is seeking a visionary Head of FPGA to lead the design and development of ultra-lowlatency trading infrastructure. This is a unique opportunity to drive hardware strategy and oversee a talented engineering team at the forefront of technological innovation. Your work … hardware engineering roadmap, with a sharp focus on ASIC design and high-performance FPGA solutions. Drive Design Excellence: Architect and oversee the development of low-latency, high-speed hardware systems that power next-generation trading platforms. Foster Collaboration: Work closely with software teams, system architects, and business stakeholders More ❯
practices for securing data and APIs, including encryption, authentication, and access control. Write scalable and performant code, optimising AWS Lambda functions and integrations for lowlatency and high throughput. Write unit tests for Lambda functions, APIs, and integration components to ensure reliability and quality of code. Work in More ❯
practices for securing data and APIs, including encryption, authentication, and access control. Write scalable and performant code, optimising AWS Lambda functions and integrations for lowlatency and high throughput. Write unit tests for Lambda functions, APIs, and integration components to ensure reliability and quality of code. Work in More ❯
practices for securing data and APIs, including encryption, authentication, and access control. Write scalable and performant code, optimising AWS Lambda functions and integrations for lowlatency and high throughput. Write unit tests for Lambda functions, APIs, and integration components to ensure reliability and quality of code. Work in More ❯
innovating the large, business-critical space of digital marketing. This involves working with multiple technologies, big data, distributed systems, machine learning, high TPS and lowlatency real-time services. The Marketing Tech Hub team will oversee the architecture, design and development of new digital marketing systems and features More ❯
rendering pipelines and associated computational requirements. Strong knowledge of rasterisation, ray tracing, and hybrid rendering approaches. Experience in designing memory systems for high-bandwidth, low-latency graphics applications. Demonstrated leadership in the architecture of complex silicon products. Proven ability to balance performance, image quality, power consumption, area, and More ❯
rendering pipelines and associated computational requirements. Strong knowledge of rasterisation, ray tracing, and hybrid rendering approaches. Experience in designing memory systems for high-bandwidth, low-latency graphics applications. Demonstrated leadership in the architecture of complex silicon products. Proven ability to balance performance, image quality, power consumption, area, and More ❯
rendering pipelines and associated computational requirements. Strong knowledge of rasterisation, ray tracing, and hybrid rendering approaches. Experience in designing memory systems for high-bandwidth, low-latency graphics applications. Demonstrated leadership in the architecture of complex silicon products. Proven ability to balance performance, image quality, power consumption, area, and More ❯
rendering pipelines and associated computational requirements. Strong knowledge of rasterisation, ray tracing, and hybrid rendering approaches. Experience in designing memory systems for high-bandwidth, low-latency graphics applications. Demonstrated leadership in the architecture of complex silicon products. Proven ability to balance performance, image quality, power consumption, area, and More ❯
rendering pipelines and associated computational requirements. Strong knowledge of rasterisation, ray tracing, and hybrid rendering approaches. Experience in designing memory systems for high-bandwidth, low-latency graphics applications. Demonstrated leadership in the architecture of complex silicon products. Proven ability to balance performance, image quality, power consumption, area, and More ❯
rendering pipelines and associated computational requirements. Strong knowledge of rasterisation, ray tracing, and hybrid rendering approaches. Experience in designing memory systems for high-bandwidth, low-latency graphics applications. Demonstrated leadership in the architecture of complex silicon products. Proven ability to balance performance, image quality, power consumption, area, and More ❯
