1 to 25 of 77 Permanent SystemVerilog Jobs in the East of England

CD.) Willing to learn new development languages, tools, frameworks and techniques. "Nice To Have" Skills and Experience: Experience in hardware functional verification (Verilog, VHDL, SystemVerilog, systemC. Using Synopsys, Cadence or Siemens tools). Knowledge of more programming languages like C, Go, JavaScript, Ruby, Perl, Tcl. Experience with Docker (images creation More ❯

Experience Defence domain experience or relevant experience in the Aerospace industry Development and certification of airborne equipment New Product Introduction experience Independent verification using SystemVerilog/UVM Experience of embedded processor cores (e.g. ARM) in FPGA designs Qualifications Honours degree or equivalent in Electronics Engineering or another STEM-based subject More ❯

DSP, or FPU architectures and debugging/testing strategies. Hands-on experience with ASIC, FPGA, and physical design tools (P&R). Proficiency in SystemVerilog, C, SystemC, C++, Python, Perl, or TCL. Knowledge of place and route methodologies. Strong communication skills, both written and spoken, in English. Who we are More ❯

/documentation Desirable Development of real-time, embedded, safety-critical firmware, preferably in accordance with RTCA/DO-254 DAL D Independent verification using SystemVerilog/UVM Relevant experience in the Aerospace or Defence industry Experience of embedded processor cores (e.g. ARM) in FPGA designs Familiarity with latest FPGA device More ❯

subject FPGA or ASIC architecture, design and verification, including: System engineering and partition IP Design, Packaging and Integration Xilinx Vivado or Altera Quartus Verilog, SystemVerilog Timing Closure Self-checking/Automated Testbenches integrated into CI Electronic design experience including high-speed design and high-level layout Technical leadership experience Knowledge More ❯

might also have experience of one or more of the following: Build systems (e.g. Bazel, Nextflow, FuseSoC) Hardware EDA tools (eg. simulation, linting, synthesis) Systemverilog, C/C++, Simulator DPI/VPI Containerization (eg. Docker) Distributed Compute, Orchestration Jenkins Automation Software templating, rendering Data Engineering/Data Science/Machine More ❯

through to the implementation and verification of these systems. Key Requirements Extensive experience working across the entire FPGA design cycle Strong command of VHDL, SystemVerilog and Xilinx design tools Solid understanding of the design of high-speed digital circuits for real-time systems and experience implementing signal processing algorithms with More ❯

through to the implementation and verification of these systems. Key Requirements Extensive experience working across the entire FPGA design cycle Strong command of VHDL, SystemVerilog and Xilinx design tools Solid understanding of the design of high-speed digital circuits for real-time systems and experience implementing signal processing algorithms with More ❯

language. Understanding of computer architecture fundamentals, such as pipelining, exception handling, memory systems. Perhaps some practical experience of working on microprocessor designs. Familiarity with SystemVerilog, maybe using a methodology such as UVM. Python programming experience, for example to automate verification flows. C++ programming experience, maybe in the context of a More ❯

language. Understanding of computer architecture fundamentals, such as pipelining, exception handling, memory systems. Perhaps some practical experience of working on microprocessor designs. Familiarity with SystemVerilog, maybe using a methodology such as UVM. Python programming experience, for example to automate verification flows. C++ programming experience, maybe in the context of a More ❯

or FPU architecture and debug/test strategies. Experience with physical implementation tools (P&R) and place-and-route flows. Programming/scripting in SystemVerilog, SystemC, C/C++, Python, Perl, or TCL. This is a chance to work on next-generation silicon that powers tomorrow’s technology! For more More ❯

or FPU architecture and debug/test strategies. Experience with physical implementation tools (P&R) and place-and-route flows. Programming/scripting in SystemVerilog, SystemC, C/C++, Python, Perl, or TCL. This is a chance to work on next-generation silicon that powers tomorrow’s technology! For more More ❯

or FPU architecture and debug/test strategies. Experience with physical implementation tools (P&R) and place-and-route flows. Programming/scripting in SystemVerilog, SystemC, C/C++, Python, Perl, or TCL. This is a chance to work on next-generation silicon that powers tomorrow’s technology! For more More ❯

CSI/DSI Experience of interconnect standards ACE, AXI, AHB, and APB Ability to form requirements and specify architectural features Expert-level Verilog/SystemVerilog for design and verification Familiarity with scripting languages (Bash, Python, Tcl, etc) The following would also be useful: Experience of Cadence simulation tool flow Experience More ❯

of own work YOU SHOULD HAVE: Over 5 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning More ❯

of verifying CPU architectures or other complex IP (e.g. GPUs, NNAs) Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Past verification ownership of multiple design blocks Analytical thinking, self-sufficiency and strong team collaboration skills Ability to work effectively More ❯

feedback and who can independently define the scope of work. Proven experience of testbench design with verification frameworks like UVM/OVM. Knowledge of SystemVerilog assertion (SVA). Exposure to different programming languages, such as C, C++ and Python. You have formal verification experience. What you can expect from us More ❯

in block-level verification using UVM or similar methodologies. Strong knowledge of coverage driven verification for complex designs. Proficient in specifying, creating, and debugging SystemVerilog/UVM constrained-random testbenches. Skilled in planning verification tasks and producing realistic effort and time estimates. Additional Qualities That Will Help Your Application Stand More ❯

a chance to contribute to industry-leading ASIC and SoC solutions in a dynamic, fast-paced environment. Key Skills & Experience Sought: Digital verification with SystemVerilog, UVM, or cocotb Computer architecture knowledge (ARM or RISC-V) Formal verification techniques Interconnect protocols: AXI or OCP ASIC design tool flows Exposure to OpenGL More ❯

a chance to contribute to industry-leading ASIC and SoC solutions in a dynamic, fast-paced environment. Key Skills & Experience Sought: Digital verification with SystemVerilog, UVM, or cocotb Computer architecture knowledge (ARM or RISC-V) Formal verification techniques Interconnect protocols: AXI or OCP ASIC design tool flows Exposure to OpenGL More ❯

a chance to contribute to industry-leading ASIC and SoC solutions in a dynamic, fast-paced environment. Key Skills & Experience Sought: Digital verification with SystemVerilog, UVM, or cocotb Computer architecture knowledge (ARM or RISC-V) Formal verification techniques Interconnect protocols: AXI or OCP ASIC design tool flows Exposure to OpenGL More ❯

computer architecture background, preferably in graphics, and a solid foundation in verification methodology will be essential to achieve high-confidence testing coverage. Description Use SystemVerilog, UVM, and C++ with industry-leading simulation tools and methodologies to verify complex GPU designs. Develop verification plans in coordination with design leads and architects. More ❯

a chance to contribute to industry-leading ASIC and SoC solutions in a dynamic, fast-paced environment. Key Skills & Experience Sought: Digital verification with SystemVerilog, UVM, or cocotb Computer architecture knowledge (ARM or RISC-V) Formal verification techniques Interconnect protocols: AXI or OCP ASIC design tool flows Exposure to OpenGL More ❯

Ability to lead technical discussions across architecture, firmware, software, and validation teams. "Nice To Have" Skills and Experience : Familiarity with RTL design, UVM/SystemVerilog, or hardware verification flows. Experience with trusted execution environments (TEEs) and secure monitor implementation. Understanding of secure firmware update mechanisms (rollback protection, anti-cloning). More ❯

Lead FPGA/Firmware Engineer Apply locations GB - Luton - Cap. Green 300 time type Full time posted on Posted 30+ Days Ago job requisition id R Job Description: Would you like to deliver the complex Firmware that forms part of More ❯