18 of 18 Permanent SystemVerilog Jobs in the East of England

Linux and/or Windows development environments . Bonus Experience Xilinx SoC platforms (e.g. Zynq, Versal) Intel (Altera) FPGA architectures, including SoCs Verilog/SystemVerilog Cryptographic algorithms or secure hardware systems Product compliance, certification, or regulated environments Personal Attributes Demonstrates ownership and accountability for technical delivery. Applies a structured approach ...

teams to optimise full-stack performance. What You’ll Need 7+ years’ FPGA/RTL design experience in timing-critical systems. Strong background in SystemVerilog, synthesis, timing closure and verification. Hands-on with Vivado/Quartus or equivalent toolchains. Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces. Nice ...

said, they are looking for the best. Senior FPGA Engineer requirements: Minimum 10+ years commercial FPGA Engineering ( Implementation, simulation, verification and test) Coding in SystemVerilog or VHDL FPGA external interface designs (e.g. PCIe, Aurora, Ethernet, SPI etc.) Strong academic background Proactive, collaborative mindset with ownership of projects Resident ...

equivalent industry experience). 6+ years’ experience in RTL design. Academic or commercial experience in CPU RTL design. Strong RTL design skills using Verilog, SystemVerilog, or VHDL. A solid software engineering background, including experience with: Object‐oriented and functional programming paradigms – C, C++, Python Compiler infrastructures, particularly domain‐specific languages ...

adjust designs to ensure timing closure - Bring value with experience in Python based verification frameworks, such as cocotb (highly advantageous) Requirements: - Strong knowledge of SystemVerilog - Experience with Python - Proven background in RTL verification - Ability to write and validate timing constraints - Understanding of low power design principles - Experience writing module specifications ...

cross‐functional hardware teams Debug challenging issues spanning RTL, simulation, and hardware platforms What they’re looking for Strong hands‐on expertise in SystemVerilog and UVM Proven debugging skills across RTL, simulation, and hardware Experience owning verification planning and strategy in commercial environments Comfortable operating in fast‐moving environments with ...

architectures Integration of operating system-class subsystems alongside real-time domains A strong appreciation of the practical realities of chip implementation, including RTL design (SystemVerilog), verification methodologies (UVM, formal, emulation/FPGA), DFT, timing closure, power analysis, and physical design constraints Familiarity with scripting languages such as Bash, Python ...

Job Description At Leonardo, we are excited to be recruiting for a skilled FPGA Engineer to work within a multi-disciplinary team for our Precision Guidance area. In this broad FPGA firmware engineering role, you ...

leading processor designs and collaborating with top architects and engineers. The role requires 6+ years in RTL design and strong skills in Verilog/SystemVerilog/VHDL, with exposure to verification methods like UVM. #J-18808-Ljbffr ...

development for large scale, high performance silicon projects. Proven success leading and developing technical teams in a semiconductor environment. Deep expertise in SystemVerilog or VHDL and familiarity with modern digital design flows. Strong ability to diagnose and resolve complex design issues, including via scripting/programming (Python, Tcl, etc.). ...

remote and occasional onsite support to VIP users in Arm offices across the world as and when required Required Skills & Experience: Experience of using SystemVerilog and UVM with sound understanding of object-oriented design, data structures and algorithms Experience of IP and SoC verification with deep knowledge of verification processes ...

Join us at Entrust. From our comprehensive portfolio of solutions to our flexible, global workplace, we empower careers, foster collaboration, and build solutions that help keep the world moving safely. Position Overview Provides technical leadership ...

senior level engineers. This award-winning Technology company seeks a Degree qualified FPGA Design Engineer with SoC design and Integration skills, RTL Verification experience (SystemVerilog, VHDL) and Python knowledge. In this role the successful Digital FPGA Design Engineer will work closely with hardware, software and mechanical engineers to bring exciting … Engineering or related discipline. Proven commercial FPGA Design experience. SoC design and Integration experience. Python knowledge ideally with exposure to cocotb. RTL Verification experience (SystemVerilog, VHDL). Experience writing timing constraints and ensuring these are met. Designing for low power. To find out more, please apply in confidence now. ...

senior level engineers. This award-winning Technology company seeks a Degree qualified FPGA Design Engineer with SoC design and Integration skills, RTL Verification experience (SystemVerilog, VHDL) and Python knowledge. In this role the successful Digital FPGA Design Engineer will work closely with hardware, software and mechanical engineers to bring exciting … Engineering or related discipline. Proven commercial FPGA Design experience. SoC design and Integration experience. Python knowledge ideally with exposure to cocotb. RTL Verification experience (SystemVerilog, VHDL). Experience writing timing constraints and ensuring these are met. Designing for low power. To find out more, please apply in confidence now. ...

Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi‐chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams test plans … Engineering or Computer Science 6+ years and current hands‐on experience in block‐level/IP‐level/SoC‐level verification Proficiency in Verilog, SystemVerilog Familiarity with industry‐standard EDA tools for simulation and debug Deep experience with UVM‐based testbenches Experience with modern programming languages like Python Knowledge ...

Lead the creation and verification of reusable RTL components A well-established company is seeking an RTL Design Architect with strong expertise in verification and good management skills to join their Cambridge-based development team. ...

work alongside experienced engineers, helping to develop robust verification environments while gaining exposure to production silicon and advanced verification methodologies. Responsibilities Develop and debug SystemVerilog/UVM testbenches. Create and execute verification plans, tests, and coverage. Debug simulation failures and support regression testing. Contribute to verification infrastructure and automation. Collaborate … quality silicon. Participate in code reviews and contribute to open-source projects. Requirements Essential 15 years' industry experience in Digital Design Verification. Experience with SystemVerilog and UVM. Understanding of verification methodologies and constrained-random verification. Experience writing testbenches and debugging RTL. Programming experience in Python and/or C. Familiarity ...

work alongside experienced engineers, helping to develop robust verification environments while gaining exposure to production silicon and advanced verification methodologies. Responsibilities Develop and debug SystemVerilog/UVM testbenches. Create and execute verification plans, tests, and coverage. Debug simulation failures and support regression testing. Contribute to verification infrastructure and automation. Collaborate … quality silicon. Participate in code reviews and contribute to open-source projects. Requirements Essential 15 years' industry experience in Digital Design Verification. Experience with SystemVerilog and UVM. Understanding of verification methodologies and constrained-random verification. Experience writing testbenches and debugging RTL. Programming experience in Python and/or C. Familiarity ...