3 of 3 Permanent ASIC Jobs in Ely

ASIC Design Engineer Cambridge Senior OR Principal Engineering level I am seeking an experienced ASIC Design Engineer to join an innovative HW team. The work of the whole ASIC team includes Architecture, considering software/hardware trade-offs, RTL design, Verification at block and system level, FPGA platforms for software development and extended verification as well as implementation including DFT … synthesis, place and route, timing closure, and sign-off checks. Due to growth, the company are expanding and seeking an ASIC Design Engineer to join an already talented group of Engineers. They are looking to expand the team in Cambridge with this role and are seeking an Engineer with working autonomously. Responsibilities Design, IP integration, and verification planning and execution. More ❯

Master's degree in Electrical Engineering, Computer Engineering, or a related field Strong understanding of hardware verification methodologies and tools Experience with UVM (Universal Verification Methodology) for FPGA/ASIC verification Familiarity with security features and protocols, such as CHERI, is a plus Excellent communication skills and the ability to work effectively in a collaborative, multidisciplinary team Day-to-day More ❯

Senior DFT Engineer – Join a World-Class ASIC Design Team in Cambridge! Are you a seasoned DFT Engineer with a drive for innovation and a passion for silicon design? This is a rare opportunity to join a cutting-edge ASIC team based in Cambridge , renowned for its pioneering work and collaborative approach to product development. As a Senior DFT Engineer … you will work on state-of-the-art ASIC projects, influencing the full design lifecycle while advancing your technical and leadership skills in a dynamic and forward-thinking environment. Role Overview In this role, you'll take the lead in developing and implementing Design-for-Test (DFT) strategies across a wide range of silicon technologies. You’ll work alongside cross … debug simulation environments. Work with advanced EDA tools for simulation (both behavioral and gate-level) and BIST integration. Skills: Strong industry experience in DFT architecture , implementation, and verification within ASIC or SoC development flows. Hands-on expertise in scan stitching, ATPG, boundary scan, on-chip clocking , and DFT partitioning . Proficient in using modern DFT tools (e.g., Synopsys, Cadence, or More ❯