Design Verification Engineer
dunfermline, north east scotland, united kingdom
Hybrid / WFH Options
Hybrid / WFH Options
IC Resources
SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh, TCL, Make, Perl Power aware verification (using CPF/UPF) This position is based in Edinburgh. This is a hybrid remote position and will follow a 2+ day in-office More ❯
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