1 to 25 of 41 Permanent RISC-V Jobs in England

debuggers. + Experience patching firmware and building shims to stub out missing hardware dependencies. + Familiarity with ARM, MIPS, AArch64, PowerPC, Xtensa, RISC-V, or other embedded architectures. + Experience with niche device ecosystems, printers (HP, Lexmark, Brother), POS systems, Russian DSPs, building automation, medical devices, or similar. ...

Reverse engineer firmware from printers, industrial controllers, POS terminals, and other devices; design boot and peripheral stubs; work across ARM, MIPS, AArch64, PowerPC, RISC-V architectures with C/C++ or Rust. This is an on-site role in London. #J-18808-Ljbffr ...

lowRISC, a Cambridge-based non-profit, is seeking skilled software engineers to work on RISC-V firmware, toolchains, and embedded OS development. You will contribute across the stack, from firmware to cloud-based tests, and help advance open-source silicon building blocks. Ideal candidates have strong Rust expertise ...

Experience Hands-on experience in embedded development, ideally ARM, ideally in a product development environment Experience with soft processors, such as Nios, Microblaze, Risc-V Linux kernel and user mode software development Devops and CI/CD flow experience C, C++ and Python Experience working directly with prototype ...

initial team will be around 5 engineers, focused on: Embedded Software/Firmware: C/C++, Rust, bare-metal and low-level development RISC-V, security or cryptography experience would be highly advantageous Were also looking for a strong technical manager/team lead to head ...

activities.Experience of agile working using Atlassian tools is desirable.Experience developing software to safety standards such as IEC 60730 or similar is desirable.Experience in RISC-V is desirable.Fluent in spoken and written English.Strong communication and interpersonal skills, with the ability to work independently and within a multidisciplinary team. Able ...

ship steady. Your mission is to make SP hardware-agnostic and hardware-ready. To design and implement the HAL across x86, ARM, and RISC-V, enabling portability without compromise. As a crew member you will design HALs that tame vendor idiosyncrasies, unify interfaces, and give the kernel ...

great if you have: Synopsys ProtoCompiler and Synplify. Used simulation and debug tools such as VCS, Questa and Verdi. Prototyped Arm or RISC-V CPU subsystems. Embedded Linux bring-up on FPGA platforms. Experience with other FPGA prototyping platforms, such as Siemens proFPGA or Cadence Protium Board-level ...

Intellectual Capital Resources Ltd is seeking Verification Engineers in the United Kingdom with 8–16 years of experience to join a high‐performance team. You will define verification requirements for security features, develop UVM testbenches ...

/C++ and Python , such as gem5. Experience delivering multiple high-performance CPU silicon designs is highly desirable. Knowledge of LLVM/GCC, RISC-V or advanced packaging technologies would be advantageous. This is an excellent opportunity for a senior CPU architect to shape future‐generation processor technology ...

with ASIC and FPGA (Altera, AMD, Lattice) design.* Experience implementing digital signal processing algorithms.* Experience integrating accelerator cores into an SoC architecture (Arm, RISC-V).* Familiarity with scripting languages (Python, Tcl).* An understanding of AI workloads and AI accelerator architecture concepts.* Comfortable with version control systems ...

including but not limited to performance modeling/simulation and performance analysis tools. Expertise with CPU architectures such as Arm Architecture (AArch32, AArch64), RISC-V, x86_64, PowerPC or DSPs and engaging with pre-silicon compiler and toolchain contributions. A track record of working with industry standard compiler ...

Processor Architect; what matters is real hands‐on exposure to processor or accelerator design, through a final-year project, FPGA build, RISC-V implementation, internship, or research, plus a comfort working across disciplines and a track record of thriving in ambiguity and fast iteration. Key Requirements A degree ...

Processor Architect; what matters is real hands‐on exposure to processor or accelerator design, through a final-year project, FPGA build, RISC-V implementation, internship, or research, plus a comfort working across disciplines and a track record of thriving in ambiguity and fast iteration. Key Requirements A degree ...

integrated into CI. Model ingestion: Own how a PyTorch or ONNX model is captured, analysed and split across the AIPU's matrix and RISC‐V vector units, the host CPU and the host's accelerators (GPU, NPU, video decoder), with placement tags that users can read and override. ...

single-chip modem module where the PHY, protocol stack, and host processor share an SoC, built from vector compute engines and a RISC-V controller. You will own requirements, model link performance, challenge design choices, and reproduce results when claims require testing. #J-18808-Ljbffr ...

couple of years old, as they make technological breakthroughs in security with a product line built on CHERI technology and RISC‐V cores. I am looking for Verification Engineers between 8-16 years experience to join a talented team. You will work in an environment where ...

profit, builds production-ready open-source chips and silicon building blocks. Our software team spans firmware, toolchains, cloud infrastructure, and validation, contributing to RISC-V, OpenTitan, and related projects. We seek engineers with solid C or Rust experience, strong problem solving, and clear written and spoken English. ...

toolchains that interact directly with hardware to cloud-based infrastructure that tests our products at scale. This includes work in areas such as: RISC-V firmware and driver development. Software hardening and security tools. Embedded operating systems (in Rust and C). Compilers, code generators, and linters. Simulators … which you had to communicate and negotiate requirements with multiple stakeholders. Strong knowledge of computer architecture; some experience with assembly languages (x86, RISC-V). Familiarity with C++ and Python. Experience with build systems and reproducible tooling (e.g. Bazel, Nix, uv). Experience developing for embedded or resource ...

time systems. - Familiarity with CI/CD for embedded or systems software. - Strong knowledge of computer architecture; some experience with assembly languages (x86, RISC-V); familiarity with hardware design is a plus. - Good knowledge of Linux. - Experience contributing to open source projects. - Higher degree levels and academic research … experience are highly valued. Ideal background: RISC/RISC-V ...

time systems. - Familiarity with CI/CD for embedded or systems software. - Strong knowledge of computer architecture; some experience with assembly languages (x86, RISC-V); familiarity with hardware design is a plus. - Good knowledge of Linux. - Experience contributing to open source projects. xehkeey - Higher degree levels and academic … research experience are highly valued. Ideal background: RISC/RISC-V ...

module in which the programmable PHY, the protocol stack and the host processor functions share one SoC, built from vector compute engines, a RISC-V control subsystem, hardware accelerators and an on-chip NPU. Much of the detailed implementation is carried out with external engineering and silicon partners. … block implementation loss budget against a floating point reference; Scrutinise the real-time partitioning across vector compute engines, accelerators and RISC-V control cores: cycles per sample and per slot, scratchpad allocation, DMA and double buffering, memory bandwidth against LPDDR or DDR, the deterministic latency chain ...

hardware and software roadmap. What you’ll do Write and optimise performance‐critical ML kernels in C, with assembly where it matters (RISC‐V and our own ISA) Build the low‐level control paths that feed those kernels, including scheduling, synchronisation, and data movement Write targeted validation workloads … cycles are spent Excellent C, and a pragmatic approach to building high‐quality, maintainable low‐level code Comfortable writing and debugging optimised assembly (RISC‐V ideal) Collaborative and high‐ownership. You communicate clearly, move fast, and enjoy working through hard problems with others Computer Science, Electronic Engineering, Maths ...

reality. Through collaborative, community-driven projects like OpenTitan (the world's first open-source silicon root of trust) and Ibex (a production-grade RISC-V CPU core), we develop and maintain high-quality, verified open IP that powers secure, next-generation hardware. Our small, expert team combines deep … hardware knowledge with modern software and infrastructure practices to accelerate open silicon adoption across industry partners and the RISC-V ecosystem. Role Overview We're looking for a motivated Infrastructure Support Engineer. You'll support a compact but unusually broad infrastructure footprint that supports hardware design, security verification ...

Role Overview: Work at the forefront of open silicon and hardware security, contributing to next-generation secure ASIC/SoC designs based around RISC-V, cryptographic accelerators and hardware security IP. This is a hands-on opportunity to make a direct impact on advanced silicon architecture … controllers or cryptographic accelerators. Understanding of hardware security, including countermeasures against physical attacks such as side-channel analysis and fault injection. Experience with RISC-V or similar processor architectures. Programming experience in Python, C and/or Rust, particularly for automation, RTL generation, software interfaces, testing or system ...