Senior Digital IC Design Engineer - Cambridge Responsibilities Develop digital designs for custom IC integration, including writing IP design specifications and coding Verilog and SystemVerilog models for simulation, synthesis, and static timing analysis. Create testbenches and automated build scripts for simulation and verification. Construct automated pre-silicon verification environments and provide more »
to other systems and processors Cross-functional collaboration within a multi-discipline team Requirements: Multiple years FPGA development experience proficiency with either VHDL or Verilog Experience with RTL Design Experience with Digital Signal Processing/DSP knowledge of 4G/5G is an advantage This is an exciting position for more »
art EDA tools for DFT, design, and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools TCL scripting; Python scripting is a plus Bachelor Degree minimum required in Electronics or other related more »
to other systems and processors Cross-functional collaboration within a multi-discipline team Requirements: Multiple years FPGA development experience proficiency with either VHDL or Verilog Experience with RTL Design Experience with Digital Signal Processing/DSP knowledge of 4G/5G is an advantage This is an exciting position for more »
Stevenage, Hertfordshire, South East, United Kingdom
Henderson Scott
from concept to production. Requirements: Bachelor's degree in Electrical Engineering, Computer Engineering, or related field. Demonstrated experience in FPGA design, including VHDL or Verilog development. Excellent problem-solving skills and attention to detail. Effective communication and teamwork abilities. Benefits: £60,000 - £80,000 Salary and comprehensive benefits package Opportunity more »
or GPUs Excellent collaboration skills Outstanding written and verbal communications Preferred Qualifications Proficiency in computer/SoC architecture and performance trade-offs Knowledge of Verilog and/or VHDL and experience with simulators and waveform debugging Familiarity with RISC-V architectures and instruction sets Knowledge of script languages The Process more »
or GPUs Excellent collaboration skills Outstanding written and verbal communications Preferred Qualifications Proficiency in computer/SoC architecture and performance trade-offs Knowledge of Verilog and/or VHDL and experience with simulators and waveform debugging Familiarity with RISC-V architectures and instruction sets Knowledge of script languages The Process more »
and algorithms Model checking and/or theorem proving Experience with formal verification techniques (abstractions, constraints, coverage, equivalence checking, etc.) Knowledge of HDL languages (Verilog, SystemVerilog, VHDL) and property languages (SVA, PSL,...) Knowledge of versioning tools (Git -preferred) Practical usage of Linux Proficiency in scripting languages, e.g. Python Communicative more »
and algorithms Model checking and/or theorem proving Experience with formal verification techniques (abstractions, constraints, coverage, equivalence checking, etc.) Knowledge of HDL languages (Verilog, SystemVerilog, VHDL) and property languages (SVA, PSL,...) Knowledge of versioning tools (Git -preferred) Practical usage of Linux Proficiency in scripting languages, e.g. Python Communicative more »
and algorithms Model checking and/or theorem proving Experience with formal verification techniques (abstractions, constraints, coverage, equivalence checking, etc.) Knowledge of HDL languages (Verilog, SystemVerilog, VHDL) and property languages (SVA, PSL,...) Knowledge of versioning tools (Git -preferred) Practical usage of Linux Proficiency in scripting languages, e.g. Python Communicative more »
related discipline - Knowledge of 4G or 5G standards - A deep understanding of FPGA fabric and clocking resources is essential. - Proficiency in hardware programming languages (Verilog and/or VHDL) is essential - Experience with RTL-level design, simulation and verification is essential - Experience with design and implementation using Avalon and/ more »
CPU/AI accelerators ML model training, quantization, sparsity, model preprocessing etc. Software-hardware co-design PyTorch, TensorFlow NCCL, OpenMPI C/C++, Python Verilog, RTL What’s on offer? The successful Architect is most likely to achieve a six-figure salary Hybrid working Interested? This is a great opportunity more »
Greater London, England, United Kingdom Hybrid / WFH Options
Hunter Bond
academic background will contribute to every phase of a new large projects, from concept through to delivery of a working system. You’ll develop Verilog code, work closely with software engineers to help develop drivers and application software as well as working with hardware engineers to evaluate devices. With a more »
london, south east england, United Kingdom Hybrid / WFH Options
Hunter Bond
academic background will contribute to every phase of a new large projects, from concept through to delivery of a working system. You’ll develop Verilog code, work closely with software engineers to help develop drivers and application software as well as working with hardware engineers to evaluate devices. With a more »
Bristol. In order to suit the project requirement you must have experience in either of the following: At least 5 years of experience in Verilog and/or System Verilog. Experience on IP/block level Test-bench bring up on SV UVM based platform At least 5 years of more »
to solve problems. Main Responsibilities Develop digital designs for custom IC integration – this would take the form of writing IP design specifications and coding Verilog and SystemVerilog models for simulation, synthesis and static timing analysis, creating testbenches and writing automated build scripts for simulation and verification. Build automated pre-silicon … in computer science/electronic engineering or equivalent Proven record in digital IC design and verification for ASIC implementation Strong RTL coding skills in Verilog and SystemVerilog with ability to write testbenches for simulation Good knowledge of clock and reset scheme and power domain structure Good knowledge of industry-standard more »
to solve problems. Main Responsibilities Develop digital designs for custom IC integration – this would take the form of writing IP design specifications and coding Verilog and SystemVerilog models for simulation, synthesis and static timing analysis, creating testbenches and writing automated build scripts for simulation and verification. Build automated pre-silicon … in computer science/electronic engineering or equivalent Proven record in digital IC design and verification for ASIC implementation Strong RTL coding skills in Verilog and SystemVerilog with ability to write testbenches for simulation Good knowledge of clock and reset scheme and power domain structure Good knowledge of industry-standard more »
outside of IR35 paying circa £80 per hour. These roles require on site work, 4 days a week in Luton. Job requirements: VHDL or Verilog Xilinx (preferred) Modelsim/Questasim Full Lifecycle Development Previous Defence Experience Please note all applicants must be eligible for SC Clearance – Dual nationals welcome. For more »
outside of IR35 paying circa £80 per hour. These roles require on site work, 4 days a week in Luton. Job requirements: VHDL or Verilog Xilinx (preferred) Modelsim/Questasim Full Lifecycle Development Previous Defence Experience Please note all applicants must be eligible for SC Clearance – Dual nationals welcome. For more »
and maintenance and design specification of documentation Skills and Experience Required: + Deep understanding of FPGA fundamentals, fabric, and clocking resources + Proficiency in Verilog/VHDL + Experience with RTL-level design + Experience with Avalon, AXI4 etc. Bonus: + Knowledge of 4G & 5G standards + Experience with scripting more »
design Deep understanding of modern design techniques Excellent understanding of verification challenges and the ability to support verification teams to achieve closure Experience in Verilog, SystemVerilog, VHDL The company is currently relatively small, around 20+ people but you will get the opportunity to support the lead and bring this product more »
voltage regulators, switches and operational amplifiers. Experience working on highly customised Power Management architecture definition is required including experience in; Cadence Composer, Cadence Virtuoso, Verilog-AMS, C. Experience in SOI processes is an advantage. You will be a strong team player who is willing to both teach and learn where more »
design Deep understanding of modern design techniques Excellent understanding of verification challenges and the ability to support verification teams to achieve closure Experience in Verilog, SystemVerilog, VHDL The company is currently relatively small, around 20+ people but you will get the opportunity to support the lead and bring this product more »
years of direct experience in one of the following; CPU microarchitecture within CPU Load/store, cache and memory subsystems VPUs Excellent SystemVerilog/Verilog experience Knowledge of high performance and low power microarchitecture techniques and trade-offs. Low power design techniques Scripting in Python (plus)This role would suit more »
