2 of 2 Permanent UVM Jobs in Kent

profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench ...

digital hardware design for FPGA using VHDL Experience and knowledge of video processing and control law algorithms Working knowledge and experience of UVM (Universal Verification Methodology) constrained random verification ...