10 of 10 Permanent PCIe Jobs in Leicestershire

implications of hard speed transmission Scripting and automation, such as TCL and Python. Knowledge of thermal and mechanical considerations in hardware design. Experience using PCIe, CXL, RDMA, DDR4, bare metal use of high-speed transceivers, Ethernet, IP. Excellent skills in SystemVerilog/Verilog/VHDL. The company offer an excellent More ❯

development out of scope) Strong verification expertise in OSVVM/UVVM (or UVM) methodologies and test bench architecture Familiar with technologies such as AXI, PCIe, Ethernet, OCP, Wishbone, JESD204, CameraLink, SMPTE Tool experience: DOORS , Vivado, ModelSim, Diamond, Radiant, Vitis, or Propel Solid understanding of DO-254 processes (not necessarily certification More ❯

technology Proficient in schematic capture using Mentor Graphics (Siemens EDA) DxDesigner or similar tools Experience of high-speed serial communication interfaces/protocols (e.g. PCIe, Ethernet/IEEE802.3, SPI, I2C, etc.) and high-speed bus architectures (e.g. DDR3/4) Use of high-speed digital design techniques such as signal More ❯

including proficiency with SystemVerilog and UVM. Ability to think creatively about solutions outside of UVM. Experience with high-speed networking interfaces and protocols like PCIe, SERDES or Ethernet. Demonstrated ability to collaborate effectively with design teams to meet objectives. If you'd like more information, apply below More ❯

based on ARM Architecture Should be familiar with AMBA based bus protocols like CHI, AXI, AHB, APB etc., Hands on experience in integration of PCIe and Ethernet Ips Good knowledge on design static checks like CDC, RDC, CLP etc., Hands on experience on chip IO integration Desirable to have working More ❯

with SOC Environment methodology and flows. Ability to debug and also coach fellow team member to debug effectively ARM Processor and CHI working experience PCIE or DDR hands on experience Notes: System-on-Chip (SoC) verification and Intellectual Property (IP) verification both are crucial aspects of the semiconductor design process. More ❯

execution. Should have a good understanding of SoC architecture and should be able to map the Arch spec to implementation level details. Experience in PCIe and Ethernet IP integration. Hands on experience on AMBA based bus protocols. Excellent communication skills is a must. Please note: Applicants for employment in UK More ❯

based on ARM Architecture Should be familiar with AMBA based bus protocols like CHI, AXI, AHB, APB etc., Hands on experience in integration of PCIe and Ethernet Ips Good knowledge on design static checks like CDC, RDC, CLP etc., Hands on experience on chip IO integration Desirable to have working More ❯

definition in collaboration with a broader Team. The key focus of this role is in developing Software for High Speed Drivers and preferably Linux PCIe Driver Development. In addition responsibilities will be developing Software for integration and interface frameworks on CPU and GPU and also Embedded Software Development (although not … is key) The successful candidate will have a good relevant Degree and have a real passion for Software Development. In addition: High speed Linux PCIe driver development Experience working directly with prototype hardware alongside the hardware design team Production experience, including; development & validation The company offer an excellent salary in More ❯

development. You will be working with a highly skilled verification team focused on developing and validating complex SoCs using the latest ARM architecture and PCIe technologies. About the Role: As a Front-End RTL Verification Engineer , you will play a key role in the verification of SoC systems, contributing to … digital designs and ensuring first-time-right silicon. You will work across the full verification lifecycle, with a strong focus on the ARM ecosystem, PCIe integration, and GLS (Gate Level Simulation). This is a 6-month B2B contract , fully remote, and open to candidates across the UK and EU … Key Responsibilities: Perform SoC verification tasks focusing on the Client ecosystem. Execute testbenches and verification environments using SystemVerilog and UVM methodologies. Integrate and verify PCIe interfaces and work with PCIe VIPs (Verification IP). Conduct Gate Level Simulations (GLS) to ensure timing and functionality. Collaborate with cross-functional teams to More ❯