4 of 4 Permanent SystemVerilog Jobs in Lincoln

FPGA Engineer

Hiring Organisation
MASS Consultants
Location
Lincoln, Lincolnshire, East Midlands, United Kingdom
Employment Type
Permanent
Salary
£40,000
including integration with high-speed ADCs/DACs. Support test and lab evaluation using signal generators, spectrum analysers, and oscilloscopes. Implement designs using VHDL, SystemVerilog, and MATLAB/Simulink HDL Coder. Develop C/C++ software for deployment to embedded systems Use industry-standard tools such as Vivado, Quartus ...

Senior Digital ASIC Design Engineer

Hiring Organisation
IC Resources
Location
Lincoln, Lincolnshire, UK
Employment Type
Full-time
successful candidate will have: Bachelors or Masters in Electronics Engineering or a related field Solid background in Digital ASIC Design Strong Verilog/SystemVerilog skills; UVM verification knowledge is a plus Hands-on with RTL design, simulation, and technical documentation Familiar with ASIC synthesis; FPGA implementation experience is a bonus ...

Senior FPGA Engineer

Hiring Organisation
MASS Consultants
Location
Lincoln, Lincolnshire, East Midlands, United Kingdom
Employment Type
Permanent
Salary
£55,000
/DACs. Support test and lab evaluation using signal generators, spectrum analysers, and oscilloscopes. Lead or contribute to the implementation of designs using VHDL, SystemVerilog, and MATLAB/Simulink HDL Coder. Develop C/C++ software for deployment to embedded systems Use industry-standard tools such as Vivado, Quartus … signal generators and logic analysers) Desirable Experience Experience working with embedded Linux, bare-metal C drivers, or FPGA-based system integration Proficiency in VHDL, SystemVerilog, and embedded C for FPGA-host integration, control, and testing Familiarity with AXI interfaces, memory interfaces, JESD204B/C, or high-speed ADC/ ...

Design Verification Engineer

Hiring Organisation
IC Resources
Location
Lincoln, Lincolnshire, UK
Employment Type
Full-time
level verification. Key Responsibilities Develop comprehensive core verification plans based on micro-architecture and design specifications. Architect and implement robust, reusable verification environments using SystemVerilog and UVM. Create and execute constrained-random and directed tests to achieve high levels of functional and code coverage. Analyse simulation results, debug complex failures … design teams to root-cause and resolve issues. Develop and maintain Python and Perl scripts to improve verification flows and regression management. Requirements Strong SystemVerilog/UVM expertise (essential). Solid understanding of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components and interconnects. Project ...