1 to 2 of 2 Permanent UVM Jobs in London

debug and testing methodologies. Experience of System Verilog for design and/or verification. Experience or knowledge of place and route methodologies. Experience of UVM Experience of C, SystemC, C++, Python, Perl, TCL. For more information and a confidential discussion please contact Rachel Mason. more »

out of a brand new office with state of the art hardware. We are looking for a RTL verification expert to build up a UVM system and implement RTL simulations for system-level functional verification of our FPGA designs. Ideally, this candidate would be proficient with Cadence Xcelium , as this more »