Design Verification (DV) Engineer
London, United Kingdom
Hudson River Trading
functional verification for FPGA or ASIC Experience with code and functional coverage collection/analysis Experience with SystemVerilog and industry-standard frameworks such as UVM Experience with Python Comfortable in a Linux environment Familiarity with Verilator and/or Cocotb preferred C++ experience is a plus A bachelor's degree More ❯
Employment Type: Permanent
Salary: GBP Annual
Posted: