Senior RTL Design Engineer – PCIe Subsystems
- Hiring Organisation
- Jobleads-UK
- Location
- Sheffield, England, United Kingdom
define design partitions, and support engineering change orders (ECOs) through to tape-out. Required skills and experience Hands-on working knowledge of SystemVerilog or Verilog HDL for RTL design Solid understanding of RTL design techniques for complex SoC development Familiarity with industry-standard EDA tools and methodologies Experience ...