25 of 25 Permanent SystemVerilog Jobs in the South East

system architecture and documentation. Skills & Experience Field Programmable Gate Arrays and digital signal processing Proven experience in FPGA design (VHDL/Verilog/SystemVerilog). Strong background in DSP implementation and digital transceiver design. Solid understanding of digital and RF hardware principles. Familiarity with AXI bus architectures and software-controlled ...

software. Collaborate with multidisciplinary teams to deliver next-generation quantum technologies. What Were Looking For: Strong experience in FPGA programming (VHDL/Verilog/SystemVerilog) and DSP implementation. Knowledge of digital and RF hardware, with hands-on experience in embedded systems. Experience with standard hardware interfaces (I2C, SPI, UART ...

successful candidate will have: Bachelors or Masters in Electronics Engineering or a related field Solid background in Digital ASIC Design Strong Verilog/SystemVerilog skills; UVM verification knowledge is a plus Hands-on with RTL design, simulation, and technical documentation Familiar with ASIC synthesis; FPGA implementation experience is a bonus ...

successful candidate will have: Bachelors or Masters in Electronics Engineering or a related field Solid background in Digital ASIC Design Strong Verilog/SystemVerilog skills; UVM verification knowledge is a plus Hands-on with RTL design, simulation, and technical documentation Familiar with ASIC synthesis; FPGA implementation experience is a bonus ...

successful candidate will have: Bachelors or Masters in Electronics Engineering or a related field Solid background in Digital ASIC Design Strong Verilog/SystemVerilog skills; UVM verification knowledge is a plus Hands-on with RTL design, simulation, and technical documentation Familiar with ASIC synthesis; FPGA implementation experience is a bonus ...

successful candidate will have: Bachelors or Masters in Electronics Engineering or a related field Solid background in Digital ASIC Design Strong Verilog/SystemVerilog skills; UVM verification knowledge is a plus Hands-on with RTL design, simulation, and technical documentation Familiar with ASIC synthesis; FPGA implementation experience is a bonus ...

successful candidate will have: Bachelors or Masters in Electronics Engineering or a related field Solid background in Digital ASIC Design Strong Verilog/SystemVerilog skills; UVM verification knowledge is a plus Hands-on with RTL design, simulation, and technical documentation Familiar with ASIC synthesis; FPGA implementation experience is a bonus ...

successful candidate will have: Bachelors or Masters in Electronics Engineering or a related field Solid background in Digital ASIC Design Strong Verilog/SystemVerilog skills; UVM verification knowledge is a plus Hands-on with RTL design, simulation, and technical documentation Familiar with ASIC synthesis; FPGA implementation experience is a bonus ...

successful candidate will have: Bachelors or Masters in Electronics Engineering or a related field Solid background in Digital ASIC Design Strong Verilog/SystemVerilog skills; UVM verification knowledge is a plus Hands-on with RTL design, simulation, and technical documentation Familiar with ASIC synthesis; FPGA implementation experience is a bonus ...

successful candidate will have: Bachelors or Masters in Electronics Engineering or a related field Solid background in Digital ASIC Design Strong Verilog/SystemVerilog skills; UVM verification knowledge is a plus Hands-on with RTL design, simulation, and technical documentation Familiar with ASIC synthesis; FPGA implementation experience is a bonus ...

successful candidate will have: Bachelors or Masters in Electronics Engineering or a related field Solid background in Digital ASIC Design Strong Verilog/SystemVerilog skills; UVM verification knowledge is a plus Hands-on with RTL design, simulation, and technical documentation Familiar with ASIC synthesis; FPGA implementation experience is a bonus ...

offer improvements to efficiency and quality for both the design flow and the final product. Required skills: Knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products A strong skillset in delivering digital designs in the ASIC and FPGA industry Optimisation of timing and hardware resources ...

testbench issues efficiently. At least two years of professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Proficiency in Python and/or C++ for building verification infrastructure, tooling, and automation. ...

Stevenage Are you an experienced FPGA Designer who enjoys contributing to the development of complex FPGA platforms? Look no further! Join our ambitious team at MBDA and be part of a company that is at ...

designs meet performance, reliability, and maintainability requirements Hands-On FPGA Engineering Design, implement, and verify FPGA logic using VHDL and/or Verilog/SystemVerilog Work with high-speed interfaces, clocks, timing closure, and synchronization logic Integrate FPGA designs with embedded software, drivers, and system-level components Support bring … required Required Skills & Experience Strong experience in FPGA design and development in a production environment Proficiency in VHDL and/or Verilog/SystemVerilog Experience with FPGA toolchains (e.g. Xilinx/AMD, Intel/Altera) Solid understanding of: Clocking and timing constraints CDC, synchronization, and deterministic timing Debugging FPGA designs ...

Staff ASIC Design Engineer This is a rare opportunity to apply your silicon design expertise to truly cutting-edge technology. Innovation sits at the core of this organisation, which develops foundational IP for market-leading ...

level verification. Key Responsibilities Develop comprehensive core verification plans based on micro-architecture and design specifications. Architect and implement robust, reusable verification environments using SystemVerilog and UVM. Create and execute constrained-random and directed tests to achieve high levels of functional and code coverage. Analyse simulation results, debug complex failures … design teams to root-cause and resolve issues. Develop and maintain Python and Perl scripts to improve verification flows and regression management. Requirements Strong SystemVerilog/UVM expertise (essential). Solid understanding of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components and interconnects. Project ...

level verification. Key Responsibilities Develop comprehensive core verification plans based on micro-architecture and design specifications. Architect and implement robust, reusable verification environments using SystemVerilog and UVM. Create and execute constrained-random and directed tests to achieve high levels of functional and code coverage. Analyse simulation results, debug complex failures … design teams to root-cause and resolve issues. Develop and maintain Python and Perl scripts to improve verification flows and regression management. Requirements Strong SystemVerilog/UVM expertise (essential). Solid understanding of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components and interconnects. Project ...

level verification. Key Responsibilities Develop comprehensive core verification plans based on micro-architecture and design specifications. Architect and implement robust, reusable verification environments using SystemVerilog and UVM. Create and execute constrained-random and directed tests to achieve high levels of functional and code coverage. Analyse simulation results, debug complex failures … design teams to root-cause and resolve issues. Develop and maintain Python and Perl scripts to improve verification flows and regression management. Requirements Strong SystemVerilog/UVM expertise (essential). Solid understanding of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components and interconnects. Project ...

level verification. Key Responsibilities Develop comprehensive core verification plans based on micro-architecture and design specifications. Architect and implement robust, reusable verification environments using SystemVerilog and UVM. Create and execute constrained-random and directed tests to achieve high levels of functional and code coverage. Analyse simulation results, debug complex failures … design teams to root-cause and resolve issues. Develop and maintain Python and Perl scripts to improve verification flows and regression management. Requirements Strong SystemVerilog/UVM expertise (essential). Solid understanding of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components and interconnects. Project ...

level verification. Key Responsibilities Develop comprehensive core verification plans based on micro-architecture and design specifications. Architect and implement robust, reusable verification environments using SystemVerilog and UVM. Create and execute constrained-random and directed tests to achieve high levels of functional and code coverage. Analyse simulation results, debug complex failures … design teams to root-cause and resolve issues. Develop and maintain Python and Perl scripts to improve verification flows and regression management. Requirements Strong SystemVerilog/UVM expertise (essential). Solid understanding of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components and interconnects. Project ...

level verification. Key Responsibilities Develop comprehensive core verification plans based on micro-architecture and design specifications. Architect and implement robust, reusable verification environments using SystemVerilog and UVM. Create and execute constrained-random and directed tests to achieve high levels of functional and code coverage. Analyse simulation results, debug complex failures … design teams to root-cause and resolve issues. Develop and maintain Python and Perl scripts to improve verification flows and regression management. Requirements Strong SystemVerilog/UVM expertise (essential). Solid understanding of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components and interconnects. Project ...

level verification. Key Responsibilities Develop comprehensive core verification plans based on micro-architecture and design specifications. Architect and implement robust, reusable verification environments using SystemVerilog and UVM. Create and execute constrained-random and directed tests to achieve high levels of functional and code coverage. Analyse simulation results, debug complex failures … design teams to root-cause and resolve issues. Develop and maintain Python and Perl scripts to improve verification flows and regression management. Requirements Strong SystemVerilog/UVM expertise (essential). Solid understanding of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components and interconnects. Project ...

We are looking for a Mixed Signal Verification Engineer to join our fabless Semiconductor client. This role can be based either in Northamptonshire, or in Berkshire. Hybrid working (3 days a week onsite) is available ...

A Digital Design Engineer with proficiency in RTL coding and a background in the design of high speed digital circuits using advanced CMOS technologies will join the talented team of an exciting name in the ...