Permanent Functional Safety Jobs in South Wales

2 of 2 Permanent Functional Safety Jobs in South Wales

Control Systems Engineer

Usk, Gwent, United Kingdom
Humber Recruitment
multi disciplined engineers. In this role, you will be responsible for designing, developing, and maintaining control systems for a range of industrial applications. You will work closely with cross-functional teams to ensure system reliability, efficiency, and performance. This is a full-time position, based in our Usk offices with occasional travel. Design, program, and commission control systems, including … control systems to improve efficiency and reliability. Conduct system testing, validation, and performance analysis. Collaborate with mechanical, electrical, and software engineers on project development. Ensure compliance with industry standards, safety regulations, and best practices. Provide technical support, training, and documentation for system users. Degree in Electrical Engineering, Control Systems Engineering, Automation, or a related field. Functional safety More ❯
Employment Type: Permanent
Salary: GBP Annual
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Principal Verification Engineer

newport, wales, united kingdom
Platform Recruitment
a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to … Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. Excellent communication skills and a methodical, detail-focused approach. Apply to learn more More ❯
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