6 of 6 Permanent SystemVerilog Jobs in the South West

aerospace-grade sensing for commercial markets. Key skills of the FPGA Engineer: Experience in FPGA design and system integration (Xilinx/Zynq preferred) Proficient in RTL design (Verilog/SystemVerilog/VHDL) Strong experience with Vivado and SoC development flows Background in designing and tuning real-time control loops (PLLs, PI, etc.) Comfortable debugging in the lab with ILA, scopes More ❯

aerospace-grade sensing for commercial markets. Key skills of the FPGA Engineer: Experience in FPGA design and system integration (Xilinx/Zynq preferred) Proficient in RTL design (Verilog/SystemVerilog/VHDL) Strong experience with Vivado and SoC development flows Background in designing and tuning real-time control loops (PLLs, PI, etc.) Comfortable debugging in the lab with ILA, scopes More ❯

aerospace-grade sensing for commercial markets. Key skills of the FPGA Engineer: Experience in FPGA design and system integration (Xilinx/Zynq preferred) Proficient in RTL design (Verilog/SystemVerilog/VHDL) Strong experience with Vivado and SoC development flows Background in designing and tuning real-time control loops (PLLs, PI, etc.) Comfortable debugging in the lab with ILA, scopes More ❯

growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off … verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. More ❯

growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off … verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. More ❯

growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off … verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. More ❯