Senior/Staff Digital ASIC Design Engineer
- Hiring Organisation
- Intellectual Capital Resources
- Location
- Stevenage, Hertfordshire, UK
SystemVerilog RTL design and verification across the full design and synthesis flow. Familiarity with synchronous and asynchronous design, and low-power techniques. Proficiency with Cadence or equivalent design and simulation tools; scripting experience (Python, TCL, CSH) highly desirable. Compensation Base salary range: £65,000–£75,000 per year, depending ...