2 of 2 Permanent SystemVerilog Jobs in Stockport

Design Verification Engineers to join the team and help ensure first-silicon success. What You'll Do Verify AI accelerator and SoC designs Build SystemVerilog/UVM testbenches and verification environments Perform coverage-driven and assertion-based verification Debug hardware-software interactions and collaborate with architecture, RTL, and software teams … Develop scalable verification frameworks from simulation to post-silicon What We're Looking For Experience in digital IC design verification (SystemVerilog/UVM) Knowledge of Python/C++ (Perl/TCL a plus) Understanding of computer architecture, memory hierarchies, and bus protocols (AMBA/AXI, NoC) Bachelor's or Master ...

designs using advanced verification methodologies. Key responsibilities Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs Create and maintain UVM-based SystemVerilog testbenches. Write, debug, and execute test cases to verify functionality, performance, and corner cases Perform block-level and full-chip verification, including simulation, coverage analysis … continuous improvement of design and verification best practices Qualifications 5+ years' experience in digital and/or mixed-signal design verification Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Solid understanding of digital design principles, RTL design, and ASIC development flows Experience with scripting ...