2 of 2 Permanent Cadence Jobs in the Thames Valley

Knowledge Strong background in formal verification for ASIC or FPGA development Proficiency with assertion-based techniques (e.g., SVA, PSL) Experience using formal verification tools (Cadence ecosystem advantageous but not essential) Scripting skills for automation (Python, TCL, Perl or similar) Understanding of digital design, CPU/ISA concepts and common ...

skills in Python, Shell, Perl, Tcl or similar. Deep understanding of the chip design process. Proficiency building robust EDA/CAD flows. Experience with Cadence Voltus (or similar). Extensive experience across front-end and back-end digital design flows (simulation, synthesis, place & route, parasitic extraction, STA, physical verification ...