oxford district, south east england, united kingdom Hybrid / WFH Options
IC Resources
immense potential in quantum technology. The ideal Senior FPGA Engineer will have: Strong experience of FPGA implementation in real-time system contexts Proficiency in SystemVerilog or Migen Solid understanding of real-time hardware/software co-design and debugging Experience with common software languages (Python, Rust, etc.) Familiarity with version More ❯
Newbury, Berkshire, United Kingdom Hybrid / WFH Options
Siemens Mobility
PCIe, CXL, UCIe, NVMe, Ethernet, USB, DDRx, HBM, AMBA. Knowledge of controllers for one or more high-speed interface protocols Expertise in coding with SystemVerilog, and UVM is mandatory Experience with integrating commercial VIP in SV/UVM bench required. Experience with Linux and Windows environments including scripting languages. Individual More ❯
a chance to contribute to industry-leading ASIC and SoC solutions in a dynamic, fast-paced environment. Key Skills & Experience Sought: Digital verification with SystemVerilog, UVM, or cocotb Computer architecture knowledge (ARM or RISC-V) Formal verification techniques Interconnect protocols: AXI or OCP ASIC design tool flows Exposure to OpenGL More ❯
a chance to contribute to industry-leading ASIC and SoC solutions in a dynamic, fast-paced environment. Key Skills & Experience Sought: Digital verification with SystemVerilog, UVM, or cocotb Computer architecture knowledge (ARM or RISC-V) Formal verification techniques Interconnect protocols: AXI or OCP ASIC design tool flows Exposure to OpenGL More ❯
range of projects that will both challenge and develop your technical and verification skills. You will have a good understanding of different methodologies, particularly SystemVerilog, UVM and MS-UCM. You will have the ability to quickly assimilate the verification challenge and help define an effective (and pragmatic) verification strategy and More ❯
Newbury, Berkshire, United Kingdom Hybrid / WFH Options
WISE Campaign
About Us Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools More ❯
strategies, you thrive on ensuring that designs comply with protocol standards and system requirements. You are experienced in creating and examining functional coverage, writing SystemVerilog assertions, and debugging RTL and gate-level simulation failures. Your background in firmware debugging and bug tracking using software tools like Jira sets you apart. … with sales, R&D, and other field AE teams to ensure customer and Synopsys goals are met. Creating and examining functional coverage and writing SystemVerilog assertions. Debugging RTL and gate-level simulation failures and firmware. Tracking bugs using software tools such as Jira and performing code coverage analysis. The Impact … the future of the verification team. What You'll Need: In-depth understanding of verification flows, test plans, and strategies. Expertise in constrained-random SystemVerilog testbenches using UVM or VMM. Experience in creating and examining functional coverage and writing SystemVerilog assertions. Skills in debugging RTL and gate-level simulation failures More ❯
Role - DV Engineer Location:EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage More ❯
oxford district, south east england, united kingdom
Stackstudio Digital Ltd
Role - DV Engineer Location:EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage More ❯
Role - DV Engineer Location:EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage More ❯
Role - DV Engineer Location:EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage More ❯
Role - DV Engineer Location:EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage More ❯
Role - RTL Design/LeadLocation:EU/Remote Mandatory Skill: SoC Integrtion, IP integration RTL design & Coding RTL lint, RTL CDC Verilog/System Verilog Industry Experience : 5 to 10 years SoC Design engineer with experience working on SOCs based More ❯
Role - RTL Design/LeadLocation:EU/Remote Mandatory Skill: SoC Integrtion, IP integration RTL design & Coding RTL lint, RTL CDC Verilog/System Verilog Industry Experience : 5 to 10 years SoC Design engineer with experience working on SOCs based More ❯
oxford district, south east england, united kingdom
Stackstudio Digital Ltd
Role - RTL Design/LeadLocation:EU/Remote Mandatory Skill: SoC Integrtion, IP integration RTL design & Coding RTL lint, RTL CDC Verilog/System Verilog Industry Experience : 5 to 10 years SoC Design engineer with experience working on SOCs based More ❯
Role - RTL Design/LeadLocation:EU/Remote Mandatory Skill: SoC Integrtion, IP integration RTL design & Coding RTL lint, RTL CDC Verilog/System Verilog Industry Experience : 5 to 10 years SoC Design engineer with experience working on SOCs based More ❯
Role - RTL Design/LeadLocation:EU/Remote Mandatory Skill: SoC Integrtion, IP integration RTL design & Coding RTL lint, RTL CDC Verilog/System Verilog Industry Experience : 5 to 10 years SoC Design engineer with experience working on SOCs based More ❯
