6 of 6 Permanent SystemVerilog Jobs in the Thames Valley

Collaborate with multidisciplinary teams to deliver next-generation quantum technologies. What We’re Looking For: Strong experience in FPGA programming (VHDL/Verilog/SystemVerilog) and DSP implementation. Knowledge of digital and RF hardware, with hands-on experience in embedded systems. Experience with standard hardware interfaces (I2C, SPI, UART ...

The Mission At OQC, we aren’t just theorising about the future; we’re building it. Born from a philosophy of bold innovation, we’ve successfully transitioned quantum computing from an academic dream into a ...

validation, and product release. Key Responsibilities: System Architecture: Lead FPGA subsystem architecture for complex data platforms. RTL & Verification: Design/verify digital RTL (SystemVerilog/Verilog) using AMD/Xilinx toolchains. Optimization: Maximize throughput, power efficiency, resource usage, and timing closure. Integration: Collaborate with ASIC, FW, and SW teams … automation and mentor mid/senior hardware engineers. What We Need: Proven full-lifecycle FPGA design experience (architecture to hardware bring-up). Strong SystemVerilog/Verilog skills with AMD/Xilinx toolchains (Vivado/Questa). Hands-on experience with high-speed interfaces (PCIe/DMA) and lab debugging ...

cleanly into end-to-end robotics solutions.**Key Responsibilities****FPGA IP Design & Architecture*** Design, implement, and optimize high-performance soft IP in Verilog/SystemVerilog for robotics and industrial solutions* Define and maintain low-level HAL/driver APIs that expose IP capabilities to embedded and host software* Develop … Electrical/Electronic Engineering (EEE), Computer Engineering, Computer Science, or a related discipline* Strong production experience in RTL design (Verilog and/or SystemVerilog) targeting FPGAs* Hands-on experience with RTL verification and simulation (e.g. ModelSim/Questa, VCS, or equivalent)* Proven ability to close timing and optimize resource utilization ...

delivering first-time success with complex mixed-signal ICs Metric-driven verification: planning, requirements extraction, directed & constrained-random verification, functional and code coverage analysis SystemVerilog, including SVA (SystemVerilog Assertions) Testbench design using verification frameworks such as UVM, OVM, e, or VMM Strong RTL/testbench debugging skills (including gate-level ...

chip that the whole team simulates against, a mixed‐abstraction model combining transistor‐level circuits with Verilog‐A/Verilog‐AMS and SystemVerilog real‐number behavioural blocks. These models will be derived from first‐principles mathematics and correlated against schematic and measured silicon. You will decide which blocks are represented … production Cadence flow: Virtuoso, Spectre, Xcelium and AMS Designer or similar co‐simulation environments, including parasitic extraction and post‐layout sign‐off SystemVerilog, plus MATLAB or Python/NumPy for analysis and model validation; scripting to automate model generation, checking and regression Cryogenic, space or other extreme‐environment silicon experience ...