1 to 25 of 57 Permanent SystemVerilog Jobs in the UK

that are degree qualified (or equivalent) with significant experience in FPGA development. Competent VHDL Language and Design Skills. Competent Verification Skills using VHDL and SystemVerilog methodologies A deep proven level of experience designing for Xilinx, Intel or Microsemi FPGAs Experience of professionally configuring and documenting designs Experience of working ...

that are degree qualified (or equivalent) with significant experience in FPGA development. Competent VHDL Language and Design Skills. Competent Verification Skills using VHDL and SystemVerilog methodologies A deep proven level of experience designing for Xilinx, Intel or Microsemi FPGAs Experience of professionally configuring and documenting designs Experience of working ...

design, and implementation of FPGA solutions for high-performance, low-latency, or high-throughput systems.Provide technical direction for RTL design (VHDL/Verilog/SystemVerilog), simulation, timing closure, and hardware validation.Define and enforce design standards, IP reuse strategies, and verification methodologies.Ensure design meets performance, power, area, and reliability targets.Work closely ...

challenges. Desirable Skills (Useful but not required - ideal for more experienced applicants) Experience with Vivado, Libero, or additional Quartus tool chains. Knowledge of Verilog, SystemVerilog, or cryptographic algorithms. Exposure to UVM/OSVVM or Assertion Based Verification. Understanding of networking protocols (Layer 2/3), USB 3.2, or NVMe. Background ...

with firmware, software and infrastructure teams to optimise full-stack performance.Requirements:7+ years FPGA/RTL design experience in timing-critical systems.Strong background in SystemVerilog, synthesis, timing closure and verification.Hands-on with Vivado/Quartus or equivalent toolchains.Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces.Bonus skills for aSenior ...

software and infrastructure teams to optimise full-stack performance. Requirements: 7+ years FPGA/RTL design experience in timing-critical systems. Strong background in SystemVerilog, synthesis, timing closure and verification. Hands-on with Vivado/Quartus or equivalent toolchains. Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces. Bonus ...

system architecture and documentation. Skills & Experience Field Programmable Gate Arrays and digital signal processing Proven experience in FPGA design (VHDL/Verilog/SystemVerilog). Strong background in DSP implementation and digital transceiver design. Solid understanding of digital and RF hardware principles. Familiarity with AXI bus architectures and software-controlled ...

system architecture and documentation. Skills & Experience Field Programmable Gate Arrays and digital signal processing Proven experience in FPGA design (VHDL/Verilog/SystemVerilog). Strong background in DSP implementation and digital transceiver design. Solid understanding of digital and RF hardware principles. Familiarity with AXI bus architectures and software-controlled ...

field (Bachelor's or Master's) Proven track record of delivering FPGA designs in complex digital systems Proficient in HDL (VHDL/Verilog/SystemVerilog) and FPGA design toolchains (Xilinx Vivado, Intel Quartus, or similar) Strong knowledge of timing closure, simulation, verification, and hardware debugging tools Experience in image/ ...

test) Strong background in Digital Signal Processing (DSP) design and optimisation Excellent academic background with a degree from a top university Proficiency in SystemVerilog or VHDL Proven ability to take technical ownership, collaborate effectively, and deliver complex projects Position: Senior FPGA Engineer Location: Cambridge Salary: £70k–£120k + equity ...

high-integrity engineering domains. Strong communication skills and ability to work within structured engineering processes. Technical Knowledge Beneficial to the Role VHDL , Verilog or SystemVerilog for digital design and implementation. Verification testbench architecture using SystemVerilog or C++ . Advanced verification methodologies such as OSVVM , UVVM or advanced VHDL verification techniques. ...

complex IP and SoC designs, owning test plans, driving coverage closure, and supporting integration using industry-standard verification environments.Key ResponsibilitiesDesign and implement UVM/SystemVerilog verification environmentsDeliver constrained-random verification and achieve coverage sign-offVerify high-speed interfaces including Ethernet (100G) and PCIe (Gen4/Gen5)Integrate and use Verification ...

complex IP and SoC designs, owning test plans, driving coverage closure, and supporting integration using industry-standard verification environments.Key ResponsibilitiesDesign and implement UVM/SystemVerilog verification environmentsDeliver constrained-random verification and achieve coverage sign-offVerify high-speed interfaces including Ethernet (100G) and PCIe (Gen4/Gen5)Integrate and use Verification ...

offer improvements to efficiency and quality for both the design flow and the final product. Required skills: Knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products A strong skillset in delivering digital designs in the ASIC and FPGA industry Optimisation of timing and hardware resources ...

offer improvements to efficiency and quality for both the design flow and the final product. Required skills: Knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products A strong skillset in delivering digital designs in the ASIC and FPGA industry Optimisation of timing and hardware resources ...

quality Qualifications Bachelor's or Master's in Electrical Engineering (or related field) Strong experience in ASIC verification and digital hardware design Skilled in SystemVerilog/UVM testbench development Knowledge of low-power verification techniques Familiarity with C for testbench development is a plus Experience in WiFi/wireless ...

quality Qualifications Bachelor's or Master's in Electrical Engineering (or related field) Strong experience in ASIC verification and digital hardware design Skilled in SystemVerilog/UVM testbench development Knowledge of low-power verification techniques Familiarity with C for testbench development is a plus Experience in WiFi/wireless ...

quality Qualifications Bachelor’s or Master’s in Electrical Engineering (or related field) Strong experience in ASIC verification and digital hardware design Skilled in SystemVerilog/UVM testbench development Knowledge of low-power verification techniques Familiarity with C for testbench development is a plus Experience in WiFi/wireless ...

Electrical Engineering, Computer Engineering, or Computer Science 5+ years’ hands-on experience in microarchitecture and RTL development Strong proficiency in Verilog and SystemVerilog Familiarity with industry-standard EDA tools and methodologies Experience with large, high-speed, pipelined, and low-power designs Deep understanding of on-chip interconnects and NoCs Experience ...

Design Engineer? Developing complex FPGA architectures and design implementations using VHDL, Simulink, targeting Xilinx, Intel, and Microsemi devices. Verifying FPGA implementations using VHDL and SystemVerilog/UVM test-bench methodologies. Utilizing FPGA design toolsets and Mentor verification tools such as QuestaSim and ModelSim. Writing low-level software … Design Engineer? Degree-qualified (or equivalent) with significant experience in FPGA development. Strong VHDL language and design skills. Proven verification skills using VHDL and SystemVerilog methodologies. Demonstrable experience designing for Xilinx, Intel, or Microsemi FPGAs. Experience in professionally configuring and documenting designs. Experience working in large, multidiscipline teams. My client ...

testbench issues efficiently. At least two years of professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Proficiency in Python and/or C++ for building verification infrastructure, tooling, and automation. ...

testbench issues efficiently. At least two years of professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Proficiency in Python and/or C++ for building verification infrastructure, tooling, and automation. ...

/DACs. Support test and lab evaluation using signal generators, spectrum analysers, and oscilloscopes. Lead or contribute to the implementation of designs using VHDL, SystemVerilog, and MATLAB/Simulink HDL Coder. Develop C/C++ software for deployment to embedded systems Use industry-standard tools such as Vivado, Quartus … signal generators and logic analysers) Desirable Experience Experience working with embedded Linux, bare-metal C drivers, or FPGA-based system integration Proficiency in VHDL, SystemVerilog, and embedded C for FPGA-host integration, control, and testing Familiarity with AXI interfaces, memory interfaces, JESD204B/C, or high-speed ADC/ ...

Job Title: FPGA Engineer Location: Luton – Hybrid 3+ days on-site per week (with some travel potential) Role Type: Contract Duration : 12 months Rate: £60.00 - £80.00 per hour – Inside IR35 Our client, an established engineering ...

Job Title: FPGA Engineer Location: Luton – Hybrid 3+ days on-site per week (with some travel potential) Role Type: Contract Duration: 12 months Rate: £60.00 - £80.00 per hour – Inside IR35 Our client, an established engineering ...