1 to 25 of 66 Permanent SystemVerilog Jobs in the UK

and skills Bachelor’s or Master’s degree in Electronic Engineering (or related field) Experience in digital ASIC design and verification, including: Defining functional requirements for verification environments & metrics SystemVerilog UVM testbenches Formal proof verification Understanding of C test cases and C code Scripting languages (e.g. Python, Perl, TCL) Desirable skills Experience with formal verification tools (JasperGold, VC Formal) Familiarity More ❯

Qualifications & Skills Bachelor’s or Master’s degree in Electronic Engineering (or related field) Experience in digital ASIC design and verification, including: Defining functional requirements for verification environments & metrics SystemVerilog UVM testbenches Formal proof verification Understanding of C test cases and C code Scripting languages (e.g. Python, Perl, TCL) Desirable Skills Experience with formal verification tools (JasperGold, VC Formal) Familiarity More ❯

Qualifications & Skills Bachelor’s or Master’s degree in Electronic Engineering (or related field) Experience in digital ASIC design and verification, including: Defining functional requirements for verification environments & metrics SystemVerilog UVM testbenches Formal proof verification Understanding of C test cases and C code Scripting languages (e.g. Python, Perl, TCL) Desirable Skills Experience with formal verification tools (JasperGold, VC Formal) Familiarity More ❯

aerospace-grade sensing for commercial markets. Key skills of the FPGA Engineer: Experience in FPGA design and system integration (Xilinx/Zynq preferred) Proficient in RTL design (Verilog/SystemVerilog/VHDL) Strong experience with Vivado and SoC development flows Background in designing and tuning real-time control loops (PLLs, PI, etc.) Comfortable debugging in the lab with ILA, scopes More ❯

or a related engineering discipline. Solid experience across the digital IC design flow, from RTL through verification to evaluation. Strong skills in RTL design, logic synthesis, and verification methodologies (SystemVerilog/UVM desirable). Familiarity with block-level physical design techniques is beneficial. Proficiency in scripting languages such as Python, Tcl, and MATLAB. Comfortable working in a Linux-based development More ❯

or a related engineering discipline. Solid experience across the digital IC design flow, from RTL through verification to evaluation. Strong skills in RTL design, logic synthesis, and verification methodologies (SystemVerilog/UVM desirable). Familiarity with block-level physical design techniques is beneficial. Proficiency in scripting languages such as Python, Tcl, and MATLAB. Comfortable working in a Linux-based development More ❯

interview, you may be asked about: Development of real-time, embedded, safety-critical FPGA, preferably in accordance with RTCA/DO-254 DAL A or B Independent verification using SystemVerilog/UVM Experience of embedded processor cores (e.g. ARM) in FPGA designs Sounds like you? Apply now or WhatsApp/ring Lukas - 07912 465 208/0161 519 8368 Working More ❯

interview, you may be asked about: Development of real-time, embedded, safety-critical FPGA, preferably in accordance with RTCA/DO-254 DAL A or B Independent verification using SystemVerilog/UVM Experience of embedded processor cores (e.g. ARM) in FPGA designs Sounds like you? Apply now or WhatsApp/ring Lukas - 07912 465 208/0161 519 8368 Working More ❯

interview, you may be asked about: Development of real-time, embedded, safety-critical FPGA, preferably in accordance with RTCA/DO-254 DAL A or B Independent verification using SystemVerilog/UVM Experience of embedded processor cores (e.g. ARM) in FPGA designs Sounds like you? Apply now or WhatsApp/ring Lukas - 07912 465 208/0161 519 8368 Working More ❯

interview, you may be asked about: Development of real-time, embedded, safety-critical FPGA, preferably in accordance with RTCA/DO-254 DAL A or B Independent verification using SystemVerilog/UVM Experience of embedded processor cores (e.g. ARM) in FPGA designs Sounds like you? Apply now or WhatsApp/ring Lukas - 07912 465 208/0161 519 8368 Working More ❯

strategies, and Agile development practices. Work closely with software and ML engineers to deliver efficient, scalable inference applications. Were looking for someone with: 5+ years experience writing well-documented SystemVerilog/Verilog/VHDL. Strong FPGA toolchain knowledge (Quartus, Vivado, or equivalent). Experience in debugging, bring-up, and timing optimisation of FPGA designs. Exposure to C/C++ or More ❯

design lifecycle, and join a team passionate about solving complex performance bottlenecks in real-world AI systems. Key skills required: Full FPGA design lifecycle experience RTL design in Verilog, SystemVerilog and/or VHDL Proficiency in C, C++ or Python for hardware-software integration Familiarity with Quartus, Vivado or similar toolchains Experience optimising RTL for performance and resource usage Comfortable More ❯

CE), Electrical Engineering (EE), Computer Science (CS), or a related technical field. Prior experience in designing, coding, testing, and verifying FPGAs and/or ASICs. Proficiency in VHDL, Verilog, SystemVerilog, as well as C or C++ programming languages. Familiarity with RTL synthesis and the ability to write timing, area, and other pertinent constraints. Experience working with digital simulators and self More ❯

CE), Electrical Engineering (EE), Computer Science (CS), or a related technical field. Prior experience in designing, coding, testing, and verifying FPGAs and/or ASICs. Proficiency in VHDL, Verilog, SystemVerilog, as well as C or C++ programming languages. Familiarity with RTL synthesis and the ability to write timing, area, and other pertinent constraints. Experience working with digital simulators and self More ❯

CE), Electrical Engineering (EE), Computer Science (CS), or a related technical field. Prior experience in designing, coding, testing, and verifying FPGAs and/or ASICs. Proficiency in VHDL, Verilog, SystemVerilog, as well as C or C++ programming languages. Familiarity with RTL synthesis and the ability to write timing, area, and other pertinent constraints. Experience working with digital simulators and self More ❯

CE), Electrical Engineering (EE), Computer Science (CS), or a related technical field. Prior experience in designing, coding, testing, and verifying FPGAs and/or ASICs. Proficiency in VHDL, Verilog, SystemVerilog, as well as C or C++ programming languages. Familiarity with RTL synthesis and the ability to write timing, area, and other pertinent constraints. Experience working with digital simulators and self More ❯

CE), Electrical Engineering (EE), Computer Science (CS), or a related technical field. Prior experience in designing, coding, testing, and verifying FPGAs and/or ASICs. Proficiency in VHDL, Verilog, SystemVerilog, as well as C or C++ programming languages. Familiarity with RTL synthesis and the ability to write timing, area, and other pertinent constraints. Experience working with digital simulators and self More ❯

bachelor’s degree in electronic engineering or a related field. At least 3+ years of commercial FPGA and general hardware design experience. Proficient in FPGA design using VHDL/SystemVerilog with AMD (Xilinx), Lattice, or Intel (Altera) products. Familiar with high-speed interfaces and advanced simulation methods. Strong communication skills for effective collaboration with team members and clients. What we More ❯

software technologies that could enhance the firm’s trading capabilities. Ideal Candidates Professional experience in FPGA/ASIC development and digital logic design. Strong proficiency with hardware description languages (SystemVerilog, Verilog, or VHDL). Solid understanding of digital design principles and verification methodologies. Experience with FPGA toolchains and flows for design, synthesis, simulation, and debugging. Knowledge of C++ and familiarity More ❯

software technologies that could enhance the firm’s trading capabilities. Ideal Candidates Professional experience in FPGA/ASIC development and digital logic design. Strong proficiency with hardware description languages (SystemVerilog, Verilog, or VHDL). Solid understanding of digital design principles and verification methodologies. Experience with FPGA toolchains and flows for design, synthesis, simulation, and debugging. Knowledge of C++ and familiarity More ❯

software technologies that could enhance the firm’s trading capabilities. Ideal Candidates Professional experience in FPGA/ASIC development and digital logic design. Strong proficiency with hardware description languages (SystemVerilog, Verilog, or VHDL). Solid understanding of digital design principles and verification methodologies. Experience with FPGA toolchains and flows for design, synthesis, simulation, and debugging. Knowledge of C++ and familiarity More ❯

software technologies that could enhance the firm’s trading capabilities. Ideal Candidates Professional experience in FPGA/ASIC development and digital logic design. Strong proficiency with hardware description languages (SystemVerilog, Verilog, or VHDL). Solid understanding of digital design principles and verification methodologies. Experience with FPGA toolchains and flows for design, synthesis, simulation, and debugging. Knowledge of C++ and familiarity More ❯

software technologies that could enhance the firm’s trading capabilities. Ideal Candidates Professional experience in FPGA/ASIC development and digital logic design. Strong proficiency with hardware description languages (SystemVerilog, Verilog, or VHDL). Solid understanding of digital design principles and verification methodologies. Experience with FPGA toolchains and flows for design, synthesis, simulation, and debugging. Knowledge of C++ and familiarity More ❯

tuning Define and contribute to verification strategies, automation flows, and CI pipelines Collaborate with cross-functional teams on architecture and system co-design Ideal profile: Extensive RTL design experience (SystemVerilog/VHDL) with a focus on performance and timing closure Hands-on with Vivado, Xilinx SoCs, and high-speed interface protocols (AXI, PCIe, SPI, I2C) Strong background in FPGA-based More ❯

tuning Define and contribute to verification strategies, automation flows, and CI pipelines Collaborate with cross-functional teams on architecture and system co-design Ideal profile: Extensive RTL design experience (SystemVerilog/VHDL) with a focus on performance and timing closure Hands-on with Vivado, Xilinx SoCs, and high-speed interface protocols (AXI, PCIe, SPI, I2C) Strong background in FPGA-based More ❯