20 of 20 Permanent Verilog Jobs in the West Midlands

up culture. Senior FPGA Engineer essential requirements At least 5+ years relevant FPGA experience Good understanding of the PCIe spec OR very experienced designer of FPGA cores. Familiarity with Verilog, System Verilog Senior FPGA Engineer desirable skills High-speed protocols Ethernet, PCIe, USB, NVMe, CXL etc C/C++. Linux, Bash, Python, VHDL, tcl Jira, Git VHDL High speed transceivers … Memory controllers PCB Layout Position : Senior FPGA Engineer Location : WFH within reach of Portsmouth Salary : £60-95k Benefits: Bonus, Pension, Healthcare Key Skills : FPGA design, Verilog Apply: jamie AT enterpriserecruitment DOT com JBRP1_UKTJ More ❯

up culture. Senior FPGA Engineer essential requirements At least 5+ years relevant FPGA experience Good understanding of the PCIe spec OR very experienced designer of FPGA cores. Familiarity with Verilog, System Verilog Senior FPGA Engineer desirable skills High-speed protocols Ethernet, PCIe, USB, NVMe, CXL etc C/C++. Linux, Bash, Python, VHDL, tcl Jira, Git VHDL High speed transceivers … Memory controllers PCB Layout Position : Senior FPGA Engineer Location : WFH within reach of Portsmouth Salary : £60-95k Benefits: Bonus, Pension, Healthcare Key Skills : FPGA design, Verilog Apply: jamie AT enterpriserecruitment DOT com JBRP1_UKTJ More ❯

up culture. Senior FPGA Engineer essential requirements At least 5+ years relevant FPGA experience Good understanding of the PCIe spec OR very experienced designer of FPGA cores. Familiarity with Verilog, System Verilog Senior FPGA Engineer desirable skills High-speed protocols Ethernet, PCIe, USB, NVMe, CXL etc C/C++. Linux, Bash, Python, VHDL, tcl Jira, Git VHDL High speed transceivers … Memory controllers PCB Layout Position : Senior FPGA Engineer Location : WFH within reach of Portsmouth Salary : £60-95k Benefits: Bonus, Pension, Healthcare Key Skills : FPGA design, Verilog Apply: jamie AT enterpriserecruitment DOT com JBRP1_UKTJ More ❯

up culture. Senior FPGA Engineer essential requirements At least 5+ years relevant FPGA experience Good understanding of the PCIe spec OR very experienced designer of FPGA cores. Familiarity with Verilog, System Verilog Senior FPGA Engineer desirable skills High-speed protocols Ethernet, PCIe, USB, NVMe, CXL etc C/C++. Linux, Bash, Python, VHDL, tcl Jira, Git VHDL High speed transceivers … Memory controllers PCB Layout Position : Senior FPGA Engineer Location : WFH within reach of Portsmouth Salary : £60-95k Benefits: Bonus, Pension, Healthcare Key Skills : FPGA design, Verilog Apply: jamie AT enterpriserecruitment DOT com JBRP1_UKTJ More ❯

up culture. Senior FPGA Engineer essential requirements At least 5+ years relevant FPGA experience Good understanding of the PCIe spec OR very experienced designer of FPGA cores. Familiarity with Verilog, System Verilog Senior FPGA Engineer desirable skills High-speed protocols Ethernet, PCIe, USB, NVMe, CXL etc C/C++. Linux, Bash, Python, VHDL, tcl Jira, Git VHDL High speed transceivers … Memory controllers PCB Layout Position : Senior FPGA Engineer Location : WFH within reach of Portsmouth Salary : £60-95k Benefits: Bonus, Pension, Healthcare Key Skills : FPGA design, Verilog Apply: jamie AT enterpriserecruitment DOT com JBRP1_UKTJ More ❯

up culture. Senior FPGA Engineer essential requirements At least 5+ years relevant FPGA experience Good understanding of the PCIe spec OR very experienced designer of FPGA cores. Familiarity with Verilog, System Verilog Senior FPGA Engineer desirable skills High-speed protocols Ethernet, PCIe, USB, NVMe, CXL etc C/C++. Linux, Bash, Python, VHDL, tcl Jira, Git VHDL High speed transceivers … Memory controllers PCB Layout Position : Senior FPGA Engineer Location : WFH within reach of Portsmouth Salary : £60-95k Benefits: Bonus, Pension, Healthcare Key Skills : FPGA design, Verilog Apply: jamie AT enterpriserecruitment DOT com JBRP1_UKTJ More ❯

up culture. Senior FPGA Engineer essential requirements At least 5+ years relevant FPGA experience Good understanding of the PCIe spec OR very experienced designer of FPGA cores. Familiarity with Verilog, System Verilog Senior FPGA Engineer desirable skills High-speed protocols Ethernet, PCIe, USB, NVMe, CXL etc C/C++. Linux, Bash, Python, VHDL, tcl Jira, Git VHDL High speed transceivers … Memory controllers PCB Layout Position : Senior FPGA Engineer Location : WFH within reach of Portsmouth Salary : £60-95k Benefits: Bonus, Pension, Healthcare Key Skills : FPGA design, Verilog Apply: jamie AT enterpriserecruitment DOT com JBRP1_UKTJ More ❯

up culture. Senior FPGA Engineer essential requirements At least 5+ years relevant FPGA experience Good understanding of the PCIe spec OR very experienced designer of FPGA cores. Familiarity with Verilog, System Verilog Senior FPGA Engineer desirable skills High-speed protocols Ethernet, PCIe, USB, NVMe, CXL etc C/C++. Linux, Bash, Python, VHDL, tcl Jira, Git VHDL High speed transceivers … Memory controllers PCB Layout Position : Senior FPGA Engineer Location : WFH within reach of Portsmouth Salary : £60-95k Benefits: Bonus, Pension, Healthcare Key Skills : FPGA design, Verilog Apply: jamie AT enterpriserecruitment DOT com JBRP1_UKTJ More ❯

up culture. Senior FPGA Engineer essential requirements At least 5+ years relevant FPGA experience Good understanding of the PCIe spec OR very experienced designer of FPGA cores. Familiarity with Verilog, System Verilog Senior FPGA Engineer desirable skills High-speed protocols Ethernet, PCIe, USB, NVMe, CXL etc C/C++. Linux, Bash, Python, VHDL, tcl Jira, Git VHDL High speed transceivers … Memory controllers PCB Layout Position : Senior FPGA Engineer Location : WFH within reach of Portsmouth Salary : £60-95k Benefits: Bonus, Pension, Healthcare Key Skills : FPGA design, Verilog Apply: jamie AT enterpriserecruitment DOT com JBRP1_UKTJ More ❯

junior members of staff. Due to the company looking to build a team in Malvern you will need to be located nearby. Key skills; FPGA design experience using VHDL. Verilog design experience is not essential but must be able to integrate/debug third party design components written in Verilog. Designing pipelined Digital Signal Processing blocks in FPGA. Writing automated More ❯

FPGA Engineer Location: Coventry Salary: £45,000-£50,000 We are excited to be supporting an established design consultancy who are looking to add an FPGA Engineer to their team. The role would offer the FPGA Engineer the opportunity to More ❯

verification solutions. Key Responsibilities: Perform SOC verification with a focus on ARM ecosystem and PCIe, including PCIe-VIP usage. Develop and execute test plans, test benches, and simulations using Verilog, SystemVerilog, and UVM. Conduct GLS (Gate Level Simulation) and ensure comprehensive code and functional coverage. Collaborate with onsite and offshore teams to coordinate verification activities and deliverables. Utilize GIT for … strong analytical and problem-solving skills throughout the verification process. Skills, Experience, and Abilities Required: 5 to 10 years of industry experience in SOC/IP verification. Expertise in Verilog, SystemVerilog, and UVM. Strong experience with code coverage, functional coverage, and test development. Hands-on experience with ARM ecosystem and PCIe protocols. Proficient in C/SystemVerilog and familiar with More ❯

verification solutions. Key Responsibilities: Perform SOC verification with a focus on ARM ecosystem and PCIe, including PCIe-VIP usage. Develop and execute test plans, test benches, and simulations using Verilog, SystemVerilog, and UVM. Conduct GLS (Gate Level Simulation) and ensure comprehensive code and functional coverage. Collaborate with onsite and offshore teams to coordinate verification activities and deliverables. Utilize GIT for … strong analytical and problem-solving skills throughout the verification process. Skills, Experience, and Abilities Required: 5 to 10 years of industry experience in SOC/IP verification. Expertise in Verilog, SystemVerilog, and UVM. Strong experience with code coverage, functional coverage, and test development. Hands-on experience with ARM ecosystem and PCIe protocols. Proficient in C/SystemVerilog and familiar with More ❯

verification solutions. Key Responsibilities: Perform SOC verification with a focus on ARM ecosystem and PCIe, including PCIe-VIP usage. Develop and execute test plans, test benches, and simulations using Verilog, SystemVerilog, and UVM. Conduct GLS (Gate Level Simulation) and ensure comprehensive code and functional coverage. Collaborate with onsite and offshore teams to coordinate verification activities and deliverables. Utilize GIT for … strong analytical and problem-solving skills throughout the verification process. Skills, Experience, and Abilities Required: 5 to 10 years of industry experience in SOC/IP verification. Expertise in Verilog, SystemVerilog, and UVM. Strong experience with code coverage, functional coverage, and test development. Hands-on experience with ARM ecosystem and PCIe protocols. Proficient in C/SystemVerilog and familiar with More ❯

verification solutions. Key Responsibilities: Perform SOC verification with a focus on ARM ecosystem and PCIe, including PCIe-VIP usage. Develop and execute test plans, test benches, and simulations using Verilog, SystemVerilog, and UVM. Conduct GLS (Gate Level Simulation) and ensure comprehensive code and functional coverage. Collaborate with onsite and offshore teams to coordinate verification activities and deliverables. Utilize GIT for … strong analytical and problem-solving skills throughout the verification process. Skills, Experience, and Abilities Required: 5 to 10 years of industry experience in SOC/IP verification. Expertise in Verilog, SystemVerilog, and UVM. Strong experience with code coverage, functional coverage, and test development. Hands-on experience with ARM ecosystem and PCIe protocols. Proficient in C/SystemVerilog and familiar with More ❯

verification solutions. Key Responsibilities: Perform SOC verification with a focus on ARM ecosystem and PCIe, including PCIe-VIP usage. Develop and execute test plans, test benches, and simulations using Verilog, SystemVerilog, and UVM. Conduct GLS (Gate Level Simulation) and ensure comprehensive code and functional coverage. Collaborate with onsite and offshore teams to coordinate verification activities and deliverables. Utilize GIT for … strong analytical and problem-solving skills throughout the verification process. Skills, Experience, and Abilities Required: 5 to 10 years of industry experience in SOC/IP verification. Expertise in Verilog, SystemVerilog, and UVM. Strong experience with code coverage, functional coverage, and test development. Hands-on experience with ARM ecosystem and PCIe protocols. Proficient in C/SystemVerilog and familiar with More ❯

verification solutions. Key Responsibilities: Perform SOC verification with a focus on ARM ecosystem and PCIe, including PCIe-VIP usage. Develop and execute test plans, test benches, and simulations using Verilog, SystemVerilog, and UVM. Conduct GLS (Gate Level Simulation) and ensure comprehensive code and functional coverage. Collaborate with onsite and offshore teams to coordinate verification activities and deliverables. Utilize GIT for … strong analytical and problem-solving skills throughout the verification process. Skills, Experience, and Abilities Required: 5 to 10 years of industry experience in SOC/IP verification. Expertise in Verilog, SystemVerilog, and UVM. Strong experience with code coverage, functional coverage, and test development. Hands-on experience with ARM ecosystem and PCIe protocols. Proficient in C/SystemVerilog and familiar with More ❯

verification solutions. Key Responsibilities: Perform SOC verification with a focus on ARM ecosystem and PCIe, including PCIe-VIP usage. Develop and execute test plans, test benches, and simulations using Verilog, SystemVerilog, and UVM. Conduct GLS (Gate Level Simulation) and ensure comprehensive code and functional coverage. Collaborate with onsite and offshore teams to coordinate verification activities and deliverables. Utilize GIT for … strong analytical and problem-solving skills throughout the verification process. Skills, Experience, and Abilities Required: 5 to 10 years of industry experience in SOC/IP verification. Expertise in Verilog, SystemVerilog, and UVM. Strong experience with code coverage, functional coverage, and test development. Hands-on experience with ARM ecosystem and PCIe protocols. Proficient in C/SystemVerilog and familiar with More ❯

verification solutions. Key Responsibilities: Perform SOC verification with a focus on ARM ecosystem and PCIe, including PCIe-VIP usage. Develop and execute test plans, test benches, and simulations using Verilog, SystemVerilog, and UVM. Conduct GLS (Gate Level Simulation) and ensure comprehensive code and functional coverage. Collaborate with onsite and offshore teams to coordinate verification activities and deliverables. Utilize GIT for … strong analytical and problem-solving skills throughout the verification process. Skills, Experience, and Abilities Required: 5 to 10 years of industry experience in SOC/IP verification. Expertise in Verilog, SystemVerilog, and UVM. Strong experience with code coverage, functional coverage, and test development. Hands-on experience with ARM ecosystem and PCIe protocols. Proficient in C/SystemVerilog and familiar with More ❯

verification solutions. Key Responsibilities: Perform SOC verification with a focus on ARM ecosystem and PCIe, including PCIe-VIP usage. Develop and execute test plans, test benches, and simulations using Verilog, SystemVerilog, and UVM. Conduct GLS (Gate Level Simulation) and ensure comprehensive code and functional coverage. Collaborate with onsite and offshore teams to coordinate verification activities and deliverables. Utilize GIT for … strong analytical and problem-solving skills throughout the verification process. Skills, Experience, and Abilities Required: 5 to 10 years of industry experience in SOC/IP verification. Expertise in Verilog, SystemVerilog, and UVM. Strong experience with code coverage, functional coverage, and test development. Hands-on experience with ARM ecosystem and PCIe protocols. Proficient in C/SystemVerilog and familiar with More ❯