1 of 1 Permanent C++ Jobs in West Sussex

and ability to work within structured engineering processes. Technical Knowledge Beneficial to the Role VHDL , Verilog or SystemVerilog for digital design and implementation. Verification testbench architecture using SystemVerilog or C++ . Advanced verification methodologies such as OSVVM , UVVM or advanced VHDL verification techniques. Requirements management using IBM DOORS . Design simulation using ModelSim or QuestaSim . FPGA development using vendor More ❯