2 of 2 Permanent SystemVerilog Jobs in Wiltshire

tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

experience in AMS (Analog Mixed-Signal) verification, mixed-signal IC design, or a related area. Proficient in at least one of the following: Verilog, SystemVerilog, or Verilog-AMS. Fundamental understanding of analog circuits, digital design flow, and mixed-signal top-level integration. Basic knowledge of PMICs, DC-DC converters ...