Staff Design Verification Engineer
- Location
- Cambridge, England, United Kingdom
ASIC verification Working experience of memory subsystems would be a plus Proficient in debugging firmware and RTL code using simulation tools Proficient in using C++ testbenches and working in Linux and Windows environment Experienced with Verilog, System Verilog, C, and C++ CPU pipeline knowledge Automating workflows in a distributed compute … environment Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands‐on experience with SystemVerilog language Scripting language experience: Perl, Ruby, Makefile, shell preferred Exposure to leadership or mentorship ...