26 to 50 of 187 Permanent Field-Programmable-Gate-Array Jobs

equipment (spectrum analysers, VNAs, signal generators) Experience in passive radar, beamforming, TDoA, Doppler, or direction finding Familiarity with embedded or real-time systems (FPGA pipelines, GPU acceleration, etc.) Programming experience in MATLAB, C++, Rust, or similar languages Knowledge of RF circuit principles (impedance matching, filter design, gain budgeting) Experience designing ...

chip lead/or SOC architect Digital/AMS, analog-mixed-signal IP End to end chip/SOC delivery experience ASIC & FPGA - verilog, system verilog, VHDL ADC/DAC - digital - analog interfaces Functional verification - system verilog - IP, system, sub-system, block, top level experience Creation of test-benches detailed ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...