76 to 86 of 86 Permanent SystemVerilog Jobs

apply today. Role: Senior IP Design EngineerType: ContractLocation: Belfast, UK Hybrid Job details:Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements. Key Skills:SystemVerilog RTL design100Gb Ethernet, PCIe Gen5, AMBA/AXIDeep understanding of FPGA/ ...

global tech firm seeking an FPGA/ASIC Hardware Engineer to design high-performance, low-latency compute systems. You’ll design RTL in SystemVerilog, optimise data pipelines, and work on advanced hardware platforms in a hands-on, performance-focused role—no industry background required. Key responsibilities: Design and develop FPGA … technologies, and architectures Contribute to a fast-moving, modern hardware development environment Key requirements: 4+ years’ experience in FPGA or ASIC RTL design Strong SystemVerilog expertise Deep understanding of FPGA/ASIC architectures and low-level hardware behaviour Experience with networking, data pipelines, or hardware acceleration (ML a plus) Working ...

within a collaborative engineering environment where innovation and engineering best practice are highly valued. Key Responsibilities - FPGA Design Engineer - Cambridge • Developing FPGA modules using SystemVerilog • Contributing reusable modules to a shared FPGA design library • RTL verification and validation • Writing and managing timing constraints • Reviewing timing reports and modifying designs … code in line with company coding standards • Collaborating with hardware, software and mechanical engineering teams Skills & Experience - FPGA Design Engineer - Cambridge • Strong experience with SystemVerilog • Experience with Python • RTL verification experience • Experience writing and managing timing constraints • Understanding of timing analysis and timing closure • Experience designing for low power ...

excellent opportunity to work on cutting-edge systems within a highly skilled and collaborative engineering environment. Key Responsibilities Design and develop FPGA modules using SystemVerilog Contribute to and maintain a shared FPGA module library Perform RTL verification and ensure robust design performance Write and maintain timing constraints , analyse timing reports … documentation reviews Ensure development aligns with established coding standards Collaborate with cross-disciplinary teams to support product development Required Skills & Experience Strong experience with SystemVerilog Experience with Python Knowledge of RTL verification methodologies Experience writing and managing FPGA timing constraints Understanding of low-power FPGA design techniques Experience producing ...

Job Title: Microarchitect & RTL Design Engineer Location: England, United Kingdom (office location yet to be determined) About the Role: We are seeking a seasoned Microarchitect and RTL Design Engineer with a strong background in microarchitecture ...

Design Verification Engineer - CPU DV/Microprocessor Verification/SystemVerilog/UVM We are partnered with a global semiconductor company with a major engineering presence in Cambridge. They are looking for a CPU Design Verification Engineer to work on high performance CPU and SoC products across a broad range ...

Role: Senior IP Design Engineer Type: Contract Location: Belfast, UK Hybrid Job details: Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements. Key Skills: SystemVerilog RTL design 100Gb Ethernet, PCIe Gen5, AMBA/AXI Deep understanding xkybehq ...

Newly created role within an R&D team at a major Semiconductor company - who have offices in Cambridge. I am looking to speaking with senior/principal level engineers who have complex experience in datapath ...

Take the initiative in developing reusable RTL for implementing clever algorithms For this role, we are seeking an academically bright candidate, PhD-qualified in a numerate stem subject such as physics, maths, electronics, or electronics ...

block- and system-level designs including RISC-V cores, cryptographic IP (OTBN), and key peripherals (USB, I2C, SPI). Key Responsibilities Develop and debug SystemVerilog/UVM testbenches Create verification plans, tests, and coverage Review contributions and resolve regressions Support CI/test infrastructure Collaborate with partners through tapeout Requirements … 5+ years industry verification experience Strong SystemVerilog and UVM Full verification lifecycle experience through tapeout C and/or Python for automation Git/GitHub collaboration Desirable: Formal verification (Jasper), RISC-V/ISA knowledge, security verification, silicon bring-up, or technical leadership experience. JBRP1_UKTJ ...

We are looking for a Mixed Signal Verification Engineer to join our fabless Semiconductor client. This role can be based either in Northamptonshire, or in Berkshire. Hybrid working (3 days a week onsite) is available ...