76 to 100 of 245 Permanent SystemVerilog Jobs

Design, develop and verify FPGA firmware for complex digital systems. Derive firmware requirements and architectures from system-level requirements. Develop RTL using Verilog/SystemVerilog and verify designs using UVM. Work with FPGA toolchains including Xilinx and Intel (Altera) devices. Develop high-speed interface solutions (e.g. PCIe, Ethernet, JESD). … testing and documentation throughout the development lifecycle. Essential Skills & Experience Strong FPGA development experience across major FPGA families. Proficiency with Xilinx tools, TCL, Verilog, SystemVerilog and UVM. Experience with Xilinx 7 Series, UltraScale, Intel (Altera) or Microsemi FPGA architectures. Knowledge of high-speed interfaces such as PCIe, Ethernet and JESD. ...

White Rabbit technology, working closely with senior engineers and multidisciplinary technical teams. Responsibilities FPGA and Embedded Development Design, develop, and verify RTL code using SystemVerilog, Verilog, VHDL and/or Migen for Xilinx Zynq and UltraScale devices. Design, develop, and verify embedded software in C and/or Rust. Support … documentation, test plans, and technical reports. Support technical investigation and problem solving across FPGA, embedded, and wider control-system interfaces. Required Qualifications Proficiency in SystemVerilog, Verilog and/or VHDL, with a solid understanding of RTL design principles. Hands-on experience with Xilinx or Altera FPGA device families. Familiarity with ...

seeks an experienced FPGA Verification Engineer to lead the verification of complex designs across multiple markets. You will develop verification strategies and architect scalable SystemVerilog/UVM environments, collaborating with hardware and software engineers throughout the lifecycle. You’ll drive structured test plans, constrained-random stimulus, and coverage with ...

seeking a Senior Verification Engineer to lead RTL verification of advanced wireless IP for ASIC and FPGA implementations. You will develop verification plans, build SystemVerilog/UVM environments and ensure coverage and quality before tape-out. The role requires 3+ years in digital verification, strong SV/UVM, Linux scripting ...

subsystems, collaborating with architecture, verification, and implementation teams to ensure high-quality, power-efficient designs. The role requires 10+ years in RTL design, strong SystemVerilog/Verilog skills, and experience with AMBA AXI/APB interfaces, SVA and UVM are advantageous. #J-18808-Ljbffr ...

subsystems, collaborating with architecture, verification, and implementation teams to ensure high-quality, power-efficient designs. The role requires 10+ years in RTL design, strong SystemVerilog/Verilog skills, and experience with AMBA AXI/APB interfaces, SVA and UVM are advantageous. #J-18808-Ljbffr ...

subsystems, collaborating with architecture, verification, and implementation teams to ensure high-quality, power-efficient designs. The role requires 10+ years in RTL design, strong SystemVerilog/Verilog skills, and experience with AMBA AXI/APB interfaces, SVA and UVM are advantageous. #J-18808-Ljbffr ...

subsystems, collaborating with architecture, verification, and implementation teams to ensure high-quality, power-efficient designs. The role requires 10+ years in RTL design, strong SystemVerilog/Verilog skills, and experience with AMBA AXI/APB interfaces, SVA and UVM are advantageous. #J-18808-Ljbffr ...

that push boundaries Drive verification efforts with a sharp focus on risk, coverage, and system-level behaviour Key skills Strong hands-on expertise in SystemVerilog and UVM Proven ability to debug across RTL, simulation, and hardware Ability to work effectively with ambiguity and changing requirements Demonstrable commercial experience in functional ...

environment and experience of multiple tape-outs Comfortable designing amplifiers, precision filters, with strong mixed-signal expertise (ADCs/DACs) Experienced in modelling using SystemVerilog, MATLAB or Python/NumPy, with strong scripting skills to automate model generation, checking and regression Able to bridge theory, simulation, and real-world hardware ...

Debug and analyse top-level design issues Codeline management, supporting multiple products & chips Review RTL implementation and mentor junior engineers Minimum Qualifications Expertise in SystemVerilog/VHDL and proficiency in revision control systems Strong problem-solving skills, ability to work across team boundaries and be productive under aggressive schedules Preferred ...

Debug and analyse top-level design issues Codeline management, supporting multiple products & chips Review RTL implementation and mentor junior engineers Minimum Qualifications Expertise in SystemVerilog/VHDL and proficiency in revision control systems Strong problem-solving skills, ability to work across team boundaries and be productive under aggressive schedules Preferred ...

record delivering complex FPGA systems from concept through to production Strong experience with RTL design, simulation, synthesis and timing analysis, including VHDL, Verilog or SystemVerilog Strong knowledge of high-speed interfaces, DSP, control logic, image processing and hardware-software co-design Excellent technical leadership, communication and stakeholder management skills, with ...

Science, or a related technical field or equivalent experience 4 years of experience with simulation-based verification methodologies and languages such as UVM and SystemVerilog or formal verification-based techniques including industry standard tools Experience developing and maintaining testbenches, test cases, and verification environments for simulation-based verification or formal ...

solver. Preferred Skills and Qualifications: Scripting experience with Python, sh/csh, TCL, MakeObject orientated programming (OOP) - Use of OOP design patternsKnowledge of SVA (SystemVerilog Assertions)Metric driven verification - verification planning, requirements extraction - Directed and constrained random verificationFunctional and code coverage analysisPower aware verification (using CPF/UPF)Testbench design ...

functional verification, including ownership of verification planning and strategy. Proven experience of testbench design with verification frameworks like UVM/OVM. Knowledge of SystemVerilog assertion (SVA). Exposure to different programming languages, such as C, C++ and Python. A proactive person who can independently define the scope of work. ...

cause analysis of issues identified throughout the verification process. Required Skills and Experience : Experience building verification environments for sophisticated RTL designs. Strong proficiency in SystemVerilog and scripting languages such as Python, Perl, or Tcl. Proven grasp of the complete verification process, starting from test planning and continuing through to verification ...

compliance. Support test and lab evaluation using signal generators, spectrum analysers, and oscilloscopes. Lead or contribute to the implementation of designs using VHDL, SystemVerilog, and MATLAB/Simulink HDL Coder. Develop low-level C software for FPGA bring-up, test, and integration. Use industry-standard tools such as Vivado, Quartus … consultation across teams. Essential Experience Proven track record in delivering FPGA designs for real-time, high-speed, or RF-centric systems. Proficiency in VHDL, SystemVerilog, and embedded C for FPGA-host integration, control, and testing. Experience with MATLAB/Simulink and HDL Coder for algorithm-to-hardware workflows. Proven ability ...

compliance. Support test and lab evaluation using signal generators, spectrum analysers, and oscilloscopes. Lead or contribute to the implementation of designs using VHDL, SystemVerilog, and MATLAB/Simulink HDL Coder. Develop low‐level C software for FPGA bring‐up, test, and integration. Use industry‐standard tools such as Vivado, Quartus … consultation across teams. Essential Experience Proven track record in delivering FPGA designs for real‐time, high‐speed, or RF‐centric systems. Proficiency in VHDL, SystemVerilog, and embedded C for FPGA‐host integration, control, and testing. Experience with MATLAB/Simulink and HDL Coder for algorithm‐to‐hardware workflows. Proven ability ...

compliance. Support test and lab evaluation using signal generators, spectrum analysers, and oscilloscopes. Lead or contribute to the implementation of designs using VHDL, SystemVerilog, and MATLAB/Simulink HDL Coder. Develop low-level C software for FPGA bring-up, test, and integration. Use industry-standard tools such as Vivado, Quartus … consultation across teams. Essential Experience Proven track record in delivering FPGA designs for real-time, high-speed, or RF-centric systems. Proficiency in VHDL, SystemVerilog, and embedded C for FPGA-host integration, control, and testing. Experience with MATLAB/Simulink and HDL Coder for algorithm-to-hardware workflows. Proven ability ...

## VHDL FPGA Firmware EngineerApplylocations: GB - Southampton: GB - Bristol - Coldharbour Lanetime type: Full timeposted on: Posted Todayjob requisition id: R0026952**Job Description:****Salary Ranges**Engineer: £38k - £53kSenior: £45k - £61kLeonardo UK operates a grade-based salary ...

Job Description:Salary RangesEngineer: £38k - £53kSenior: £45k - £61kLeonardo UK operates a grade-based salary framework with broad bands. The salary range shown reflects the approved grade band for this role, or a narrower hiring range ...

Are you an experienced FPGA Designer who enjoys contributing to the development of complex FPGA platforms? Look no further! Join our ambitious team at MBDA and be part of a company that is at the ...

Job Description:Salary RangesEngineer: £38k - £53kSenior: £45k - £61kLeonardo UK operates a grade-based salary framework with broad bands. The salary range shown reflects the approved grade band for this role, or a narrower hiring range ...

critical IP, collaborating with graphics architecture, verification and physical design teams. The role covers design flow from concept to physical handoff and requires SystemVerilog/VHDL experience; preferred knowledge in architecture and scripting languages. Apple emphasises inclusion and accessibility. #J-18808-Ljbffr ...