Knowledge of SoCs, FPGA/ASIC development, including RTL design and verification using VHDL, Verilog, and SystemVerilog. Familiarity with FPGA/ASIC development using SystemVerilog, VHDL, and Verilog for high-performance embedded applications. Familiarity with RTL synthesis, verification, and timing analysis using tools such as Xilinx Vivado, Intel Quartus, or More ❯
science Experience with ASIC/FPGA design or verification Experience with ASIC/FPGA architectural definition, and detailed design implementation and functional verification using SystemVerilog with delivery/release of production designs Experience with hardware-based integration and test of ASIC/FPGA designs Preferred Qualifications (Desired Skills/Experience More ❯
years of ASIC/FPGA design or verification experience Experience with ASIC/FPGA architectural definition, and detailed design implementation and functional verification using SystemVerilog with delivery/release of production designs Professional experience with hardware-based integration and test of ASIC/FPGA designs Proven record of leading ASIC More ❯
and development (R&D), prototyping, and system integration to support mission-critical defense projects. Develop and optimize digital logic designs using VHDL, Verilog, or SystemVerilog (C is a bonus). Work closely with hardware engineers, embedded software developers, and RF engineers to integrate FPGA designs into embedded systems. Perform simulation More ❯
and development (R&D), prototyping, and system integration to support mission-critical defense projects. Develop and optimize digital logic designs using VHDL, Verilog, or SystemVerilog (C is a bonus). Work closely with hardware engineers, embedded software developers, and RF engineers to integrate FPGA designs into embedded systems. Perform simulation More ❯
DSP, or FPU architectures and debugging/testing strategies. Hands-on experience with ASIC, FPGA, and physical design tools (P&R). Proficiency in SystemVerilog, C, SystemC, C++, Python, Perl, or TCL. Knowledge of place and route methodologies. Strong communication skills, both written and spoken, in English. Who we are More ❯
speed I/O like GTM and F-Tile transceivers Expertise in FPGA tool flows: synthesis, partitioning, place & route, timing analysis Strong skills in SystemVerilog, Verilog, VHDL, and scripting (tcl and Python) Experience with high-performance FPGA devices such as Xilinx Versal Premium or Intel Agilex 7 If you're More ❯
embedded C/C++ based SoC verification environments. Knowledge of assembly language (preferably ARM), C/C++ and/or hardware verification languages e.g. SystemVerilog, shell programming/scripting (e.g. Tcl, Perl, Python etc.). Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power More ❯
verification methodology for complex FPGAs. Ability to analyze requirements, create test plan, build and set up scalable simulation environments from the ground up using SystemVerilog/UVM Familiarity with testing complex designs, code coverage, functional coverage, assertions. Ability to work in a dynamic environment that includes working with changing needs More ❯
embedded C/C++ based SoC verification environments. Knowledge of assembly language (preferably ARM), C/C++ and/or hardware verification languages e.g. (SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.). Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power More ❯
CS), or a related technical field. 2+ years experience in designing, coding, testing, and verifying FPGAs and/or ASICs. Proficiency in VHDL, Verilog, SystemVerilog, as well as C or C++ programming languages. Familiarity with RTL synthesis and the ability to write timing, area, and other pertinent constraints. Experience working More ❯
Science (CS), or a related technical field. Prior experience in designing, coding, testing, and verifying FPGAs and/or ASICs. Proficiency in VHDL, Verilog, SystemVerilog, as well as C or C++ programming languages. Familiarity with RTL synthesis and the ability to write timing, area, and other pertinent constraints. Experience working More ❯
implementation and testing, support. Proven technical and/or team leadership skills. Practical experience of working on microprocessor designs. Desirable experience: Working knowledge of SystemVerilog Assertions (SVA). Mentoring team members. Knowledge of scripting eg Python, Perl or unix shell scripting. Knowledge of assembly language (preferably ARM), C/C++ More ❯
implementation and testing, support. Proven technical and/or team leadership skills. Practical experience of working on microprocessor designs. Desirable experience: Working knowledge of SystemVerilog Assertions (SVA). Mentoring team members. Knowledge of scripting eg Python, Perl or unix shell scripting. Knowledge of assembly language (preferably ARM), C/C++ More ❯
implementation and testing, support. Proven technical and/or team leadership skills. Practical experience of working on microprocessor designs. Desirable experience: Working knowledge of SystemVerilog Assertions (SVA). Mentoring team members. Knowledge of scripting eg Python, Perl or unix shell scripting. Knowledge of assembly language (preferably ARM), C/C++ More ❯
lifecycle - from requirements definition and architectural design to implementation, testing, and integration. What You'll Bring Proficiency with tools such as Xilinx, TCL, Verilog, SystemVerilog, and UVM. Experience with FPGA architectures including Xilinx 7, Xilinx UltraScale, Intel (Altera), or Microsemi (Actel). Knowledge of high-speed interfaces such as PCIe More ❯
Manchester, Lancashire, United Kingdom Hybrid / WFH Options
Arm Limited
embedded C/C++ based SoC verification environments. Knowledge of assembly language (preferably ARM), C/C++ and/or hardware verification languages e.g. (SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.). Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power More ❯
and testing, support Desirable Experience: Practical experience of working on GPU/microprocessor designs Knowledge of 3D Graphics - OpenGL, Vulkan, DirectX Working knowledge of SystemVerilog Assertions (SVA) Mentoring team members Experience in leading teams or projects Knowledge of scripting e.g., Python, Perl or UNIX shell scripting Experience of design for More ❯
Top-Secret security clearance Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field Experience with modern digital verification and modeling languages: SystemVerilog, SystemC, C/C++, Matlab, etc. Directed, constrained-random, and assertion-based verification techniques at the gate, interface, and transaction levels Experience with modern, commercial More ❯
IC Design expertise – Solid knowledge of ASIC/FPGA design techniques and methodologies. Hands-on RTL Design – Experience at IP or SoC level using SystemVerilog, C++, Python, Perl, or TCL . Verification Knowledge – Familiarity with UVM, formal verification, assertions, and coverage bins . Experience with GPU/CPU design – Understanding More ❯
development Experience with a coverage-driven verification methodology from planning through closure Knowledge of industry standard bus or I/O interfaces Experience with SystemVerilog Assertions (SVA) FPGA/ASIC design and/or development process experience Experience with scripting languages (Bash, Perl, Python, Tcl, Makefile) Knowledge of digital signal More ❯
FPGA Design Engineer opportunity in Lexington, MA! Required Skills: -Proficient in Verilog, SystemVerilog, VHDL and C. -Ability to take an FPGA from concept to a device that meets all functional and timing requirements. This would also include generating system level test benches to verify FPGA performance, functionality and error recovery More ❯
language. Understanding of computer architecture fundamentals, such as pipelining, exception handling, memory systems. Perhaps some practical experience of working on microprocessor designs. Familiarity with SystemVerilog, maybe using a methodology such as UVM. Python programming experience, for example to automate verification flows. C++ programming experience, maybe in the context of a More ❯
