FPGA Design Engineer - AI and HPC Networking
- Hiring Organisation
- Oriole
- Location
- London Area, United Kingdom
timing analysis). Comprehensive understanding of clock domain crossing techniques. Strong knowledge of FPGA debug tools such as JTAG/ILA. Excellent skills in SystemVerilog/Verilog/VHDL. Experience using simulation tools such as Questa, ModelSim, Vivado and Vitis. Scripting and automation, such as TCL and Python. Efficient ...