explore and implement high-performance CPU strategies. Transform high-level architectural research into detailed, implementable technical specifications. Design, assess, and refine RTL (Verilog/VHDL) to hit aggressive timing, area, and power goals. Partner with the DV team to ensure the design meets both functional correctness and performance benchmarks. Work … requirements: Thorough knowledge of areas like Instruction Fetch/Decode, Out-of-Order Execution, and Memory Subsystems. Strong proficiency in Verilog and/or VHDL and waveform debugging. Solid understanding of logic design principles and their implications on timing and power. Understanding of register renaming, instruction scheduling, and speculative execution. ...