Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs … test failures and file bug report as needed. • Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps. • Provide verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs … test failures and file bug report as needed. • Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps. • Provide verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs … test failures and file bug report as needed. • Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps. • Provide verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs … test failures and file bug report as needed. • Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps. • Provide verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal More ❯
Staff GPU VerificationEngineer UK - Hybrid - Bristol, Cambridge or Kings Langley Up to £90,000 + Annual Bonus Permanent Are you committed to developing cutting-edge devices, and building your own expertise in verification? With this role, you get a unique opportunity to exercise hardware verification skills on innovative designs within an esteemed Hardware department. You … can apply your abilities to essential aspects that meet the most recent requirements and advancements, and be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved … in the execution of all verification efforts of a component or sub-system, from the planning stage to sign-off. This will include creating verification plans, and development/maintenance of testbench components. Interested? Apply Now! 5V Tech are acting as an Employment Agency for the purposes of this job vacancy. We offer a reward scheme if you More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs … test failures and file bug report as needed. • Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps. • Provide verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal More ❯
Experienced AMS Design VerificationEngineer (m/f/d) At Apple, we work daily to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and creative Design Verification Engineer. As a member … products that will delight and encourage millions of Apple's customers every single day. Do your life's best work here at Apple! This role is for a Design Verificationengineer who will enable bug-free first silicon for the mixed-signal designs in our Munich team. The responsibilities include all phases of pre-silicon verification including … but not limited to: construction of verification environments, coding of test scenarios and assertions and close collaboration with Analog and Digital Design engineers. Description Definition and design of Self-checking verification environments for multi-layer systems using the SystemVerilog UVM library. The responsibility spans from concept discussions, verification strategy definition and execution of the verification tasks More ❯
ASIC VerificationEngineer European Tech Recruit are working closely with an exciting security semicon start-up, based in Amsterdam, who are looking for a talented ASIC VerificationEngineer to join their team. In this role you will play a critical role in verifying complex SoC architectures, ensuring they meet rigorous functional, performance, and compliance standards. This … is a hands-on role suited for someone with strong expertise in UVM-based environments and a passion for improving verification processes. Responsibilities as ASIC VerificationEngineer : Design, implement, and maintain UVM-based verification environments for advanced digital and SoC designs. Develop detailed verification plans and create targeted test cases based on functional specifications. Build … execute robust test benches to validate functionality, performance, and specification compliance. Proactively debug issues and collaborate closely with design teams to ensure timely resolution. Contribute to the evolution of verification methodologies, driving best practices and process improvements. Work cross-functionally to align verification activities with broader project goals and schedules. Participate in design and architecture reviews, offering insights More ❯
ASIC VerificationEngineer - Semiconductor - Amsterdam We've partnered with a fast-growing and innovative start-up based in Amsterdam. As the company continues to expand, they're looking for an experienced ASIC VerificationEngineer to join their team. In this role, you'll be responsible for verifying complex System-on-Chip (SoC) designs, ensuring they function … properly and meet performance and quality standards. This is a hands-on role, perfect for someone with solid UVM experience and a passion for making verification processes better. Key Responsibilities: Set up and manage UVM-based verification environments for SoC and digital designs Write test plans and test cases based on design requirements Build test benches to check … chip performance, functionality, and compliance Work closely with designers to find and fix problems early Help improve how verification is done by sharing best practices Collaborate with other teams to keep projects on track Take part in design reviews and offer input from the verification side Your profile: Degree in Electrical or Computer Engineering (Master's is a More ❯
ASIC VerificationEngineer - Semiconductor - Amsterdam We've partnered with a fast-growing and innovative start-up based in Amsterdam. As the company continues to expand, they're looking for an experienced ASIC VerificationEngineer to join their team. In this role, you'll be responsible for verifying complex System-on-Chip (SoC) designs, ensuring they function … properly and meet performance and quality standards. This is a hands-on role, perfect for someone with solid UVM experience and a passion for making verification processes better. Key Responsibilities: Set up and manage UVM-based verification environments for SoC and digital designs Write test plans and test cases based on design requirements Build test benches to check … chip performance, functionality, and compliance Work closely with designers to find and fix problems early Help improve how verification is done by sharing best practices Collaborate with other teams to keep projects on track Take part in design reviews and offer input from the verification side Your profile: Degree in Electrical or Computer Engineering (Master's is a More ❯
connectivity to IP blocks (using ASM boot , and C code, GNU toolchain ) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs/Subsystems • Run regressions, debug test failures and file bug report as needed. • Develop tests to meet … functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps. • Provide verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based More ❯
A leading quantitative trading firm is looking for a Senior FPGA Test & VerificationEngineer to join their core hardware engineering team. This group is responsible for building and validating high-performance FPGA-based trading systems used across global financial markets. This is an opportunity to work on low-latency infrastructure at the forefront of electronic trading, alongside experts … in hardware, software, and quantitative research. Key Responsibilities: Develop and lead testing and verification strategies for FPGA systems Define best practices and maintain testing standards across projects Implement simulation environments and hardware-in-the-loop testing Collaborate closely with trading and engineering teams to ensure robust, reliable systems Key Requirements: Strong experience in functional verification, including coverage models More ❯
A leading quantitative trading firm is looking for a Senior FPGA Test & VerificationEngineer to join their core hardware engineering team. This group is responsible for building and validating high-performance FPGA-based trading systems used across global financial markets. This is an opportunity to work on low-latency infrastructure at the forefront of electronic trading, alongside experts … in hardware, software, and quantitative research. Key Responsibilities: Develop and lead testing and verification strategies for FPGA systems Define best practices and maintain testing standards across projects Implement simulation environments and hardware-in-the-loop testing Collaborate closely with trading and engineering teams to ensure robust, reliable systems Key Requirements: Strong experience in functional verification, including coverage models More ❯
A leading quantitative trading firm is looking for a Senior FPGA Test & VerificationEngineer to join their core hardware engineering team. This group is responsible for building and validating high-performance FPGA-based trading systems used across global financial markets. This is an opportunity to work on low-latency infrastructure at the forefront of electronic trading, alongside experts … in hardware, software, and quantitative research. Key Responsibilities: Develop and lead testing and verification strategies for FPGA systems Define best practices and maintain testing standards across projects Implement simulation environments and hardware-in-the-loop testing Collaborate closely with trading and engineering teams to ensure robust, reliable systems Key Requirements: Strong experience in functional verification, including coverage models More ❯
london (city of london), south east england, united kingdom
NJF Global Holdings Ltd
A leading quantitative trading firm is looking for a Senior FPGA Test & VerificationEngineer to join their core hardware engineering team. This group is responsible for building and validating high-performance FPGA-based trading systems used across global financial markets. This is an opportunity to work on low-latency infrastructure at the forefront of electronic trading, alongside experts … in hardware, software, and quantitative research. Key Responsibilities: Develop and lead testing and verification strategies for FPGA systems Define best practices and maintain testing standards across projects Implement simulation environments and hardware-in-the-loop testing Collaborate closely with trading and engineering teams to ensure robust, reliable systems Key Requirements: Strong experience in functional verification, including coverage models More ❯
Job Description VerificationEngineer - Cambridge (can do remote within the UK) Senior and Principal Verification Engineers I am seeking highly skilled and detail-oriented Verification Engineers to join a dynamic start-up. The successful candidate will be responsible for applying formal methods to verify the correctness of hardware designs, ensuring that the systems meet functional specifications … and Seniors alike to join! Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. (PLUS) Proven experience with formal verification tools (e.g., Cadence JasperGold, Synopsys VC Formal, or equivalent tools). Hands-on experience with RTL design such as Verilog, SystemVerilog, or VHDL. Experience with verification methodologies such … as UVM (Universal Verification Methodology) or other simulation-based verification techniques. Experience with assertions (e.g., SVA - SystemVerilog Assertions) and formal verification environments. On offer is the chance to join an early stage start-up with a founder who has already had previous success within the Semiconductor space. You will get equity and a competitive base salary. The More ❯
an exciting time to join a growing UK based company in their UK HQ! The specific Wi-Fi IC Group is looking to strengthen their team with a Junior VerificationEngineer who has knowledge and understanding of SoC and IP level verification. This role is not limited to but would best suit someone with 1-5 years of … Verilog, SystemVerilog, UVM, C, Formal. Embedded C code or writing CPU-centric tests using C. Qualifications MSc in electrical engineering or equivalent or Bachelor with industrial experience. Knowledge of verification planning, assertion based and formal verification techniques, metric driven verification with UVM and C testbenches. Experience with low power verification and SoC level verification. You will More ❯
Social network you want to login/join with: A leading quantitative trading firm is looking for a Senior FPGA Test & VerificationEngineer to join their core hardware engineering team. This group is responsible for building and validating high-performance FPGA-based trading systems used across global financial markets. This is an opportunity to work on low-latency … infrastructure at the forefront of electronic trading, alongside experts in hardware, software, and quantitative research. Key Responsibilities: Develop and lead testing and verification strategies for FPGA systems Define best practices and maintain testing standards across projects Implement simulation environments and hardware-in-the-loop testing Collaborate closely with trading and engineering teams to ensure robust, reliable systems Key Requirements … Strong experience in functional verification, including coverage models, reusable testbenches, and randomized testing (SystemVerilog, UVM, or cocotb) Proficient in Python and C++ in a Linux environment Comfortable with CI/CD workflows (Jenkins, GitLab CI, Bamboo, etc.) Understanding of networking protocols such as TCP/IP and UDP/IP is a plus Strong analytical and problem-solving skills More ❯
ASIC VerificationEngineer (m/f/d) We are proud to be partnered a fast-growing Semiconductor start up. They are seeking an experienced ASIC VerificationEngineer to join their team in developing cutting-edge digital designs. You will play a critical role in verifying complex SoC architectures, ensuring they meet rigorous functional, performance, and … compliance standards. This is a hands-on role suited for someone with strong expertise in UVM-based environments and a passion for improving verification processes. Please not, we can only consider candidates, who are already holding an EU work permit/are eligible to work in the EU. Responsibilities Design, implement, and maintain UVM-based verification environments for … advanced digital and SoC designs. Develop detailed verification plans and create targeted test cases based on functional specifications. Build and execute robust test benches to validate functionality, performance, and specification compliance. Proactively debug issues and collaborate closely with design teams to ensure timely resolution. Contribute to the evolution of verification methodologies, driving best practices and process improvements. Work More ❯
Our client is a fast-growing Semiconductor start up. They are seeking an experienced ASIC VerificationEngineer to join their team in developing cutting-edge digital designs. You will play a critical role in verifying complex SoC architectures, ensuring they meet rigorous functional, performance, and compliance standards. This is a hands-on role suited for someone with strong … expertise in UVM-based environments and a passion for improving verification processes. Responsibilities: Design, implement, and maintain UVM-based verification environments for advanced digital and SoC designs. Develop detailed verification plans and create targeted test cases based on functional specifications. Build and execute robust test benches to validate functionality, performance, and specification compliance. Proactively debug issues and … collaborate closely with design teams to ensure timely resolution. Contribute to the evolution of verification methodologies, driving best practices and process improvements. Work cross-functionally to align verification activities with broader project goals and schedules. Participate in design and architecture reviews, offering insights from a verification standpoint. Required Qualifications and Skills: Bachelor's degree in Electrical or More ❯
Greater Bristol Area, United Kingdom Hybrid / WFH Options
Electus Recruitment Solutions
Validation and VerificationEngineer – Software-Based Systems 📍 Location: Bristol (Hybrid – 4–5 days on-site per week) 💰 Salary: Circa £55,000 DOE + bonus, flexi-leave & benefits 🛡️ Security Clearance: Sole UK or Dual British National | SC eligibility required Join a specialist Validation and Verification team working at the heart of a high-impact Command & Control (C2) system … through the full lifecycle – from requirements capture to delivery. Your Role Support the development and delivery of Command & Control (C2) software systems. Define C2 test scenarios, success criteria and verification plans. Work closely with the Design Authority to confirm the appropriate verification approach. Contribute to complex systems engineering processes that ensure end-to-end functionality of software-led … leave Enhanced parental, paternity, and fertility-related leave Subsidised meals, free on-site parking, and exceptional facilities Ongoing training and development in a mission-driven engineering environment Keywords: Systems Engineer, Systems Design, Software Systems, VerificationEngineer, Validation Engineer, Command and Control, C2 Systems, SysML, Rhapsody, DOORS, Software Validation, Defence Engineering, Software V&V, Requirements Testing, Test More ❯
newport, wales, united kingdom Hybrid / WFH Options
Electus Recruitment Solutions
Validation and VerificationEngineer – Software-Based Systems 📍 Location: Bristol (Hybrid – 4–5 days on-site per week) 💰 Salary: Circa £55,000 DOE + bonus, flexi-leave & benefits 🛡️ Security Clearance: Sole UK or Dual British National | SC eligibility required Join a specialist Validation and Verification team working at the heart of a high-impact Command & Control (C2) system … through the full lifecycle – from requirements capture to delivery. Your Role Support the development and delivery of Command & Control (C2) software systems. Define C2 test scenarios, success criteria and verification plans. Work closely with the Design Authority to confirm the appropriate verification approach. Contribute to complex systems engineering processes that ensure end-to-end functionality of software-led … leave Enhanced parental, paternity, and fertility-related leave Subsidised meals, free on-site parking, and exceptional facilities Ongoing training and development in a mission-driven engineering environment Keywords: Systems Engineer, Systems Design, Software Systems, VerificationEngineer, Validation Engineer, Command and Control, C2 Systems, SysML, Rhapsody, DOORS, Software Validation, Defence Engineering, Software V&V, Requirements Testing, Test More ❯
bath, south west england, united kingdom Hybrid / WFH Options
Electus Recruitment Solutions
Validation and VerificationEngineer – Software-Based Systems 📍 Location: Bristol (Hybrid – 4–5 days on-site per week) 💰 Salary: Circa £55,000 DOE + bonus, flexi-leave & benefits 🛡️ Security Clearance: Sole UK or Dual British National | SC eligibility required Join a specialist Validation and Verification team working at the heart of a high-impact Command & Control (C2) system … through the full lifecycle – from requirements capture to delivery. Your Role Support the development and delivery of Command & Control (C2) software systems. Define C2 test scenarios, success criteria and verification plans. Work closely with the Design Authority to confirm the appropriate verification approach. Contribute to complex systems engineering processes that ensure end-to-end functionality of software-led … leave Enhanced parental, paternity, and fertility-related leave Subsidised meals, free on-site parking, and exceptional facilities Ongoing training and development in a mission-driven engineering environment Keywords: Systems Engineer, Systems Design, Software Systems, VerificationEngineer, Validation Engineer, Command and Control, C2 Systems, SysML, Rhapsody, DOORS, Software Validation, Defence Engineering, Software V&V, Requirements Testing, Test More ❯
bradley stoke, south west england, united kingdom Hybrid / WFH Options
Electus Recruitment Solutions
Validation and VerificationEngineer – Software-Based Systems 📍 Location: Bristol (Hybrid – 4–5 days on-site per week) 💰 Salary: Circa £55,000 DOE + bonus, flexi-leave & benefits 🛡️ Security Clearance: Sole UK or Dual British National | SC eligibility required Join a specialist Validation and Verification team working at the heart of a high-impact Command & Control (C2) system … through the full lifecycle – from requirements capture to delivery. Your Role Support the development and delivery of Command & Control (C2) software systems. Define C2 test scenarios, success criteria and verification plans. Work closely with the Design Authority to confirm the appropriate verification approach. Contribute to complex systems engineering processes that ensure end-to-end functionality of software-led … leave Enhanced parental, paternity, and fertility-related leave Subsidised meals, free on-site parking, and exceptional facilities Ongoing training and development in a mission-driven engineering environment Keywords: Systems Engineer, Systems Design, Software Systems, VerificationEngineer, Validation Engineer, Command and Control, C2 Systems, SysML, Rhapsody, DOORS, Software Validation, Defence Engineering, Software V&V, Requirements Testing, Test More ❯
PhD) - Experience in HDL (VHDL/Verilog) and HVL (SystemVerilog) Required Skills: Experience in HDL (VHDL/Verilog) and HVL (SystemVerilog) Experience with SystemVerilog Assertions (SVA) Knowledge of Universal Verification Methodology (UVM) Familiarity with a coverage driven verification methodology from planning through closure Knowledge of industry standard interfaces Experience with object oriented programming languages and concepts Desired Skills … Advanced Degree either MS or PhD Experience with Mentor Graphics and/or Cadence Verification tools - FPGA/ASIC Design experience Knowledge of digital signal processing Experience with scripting languages (Bash, Perl, Python, Tcl More ❯
