experience with formal verification tools (e.g., Cadence JasperGold, Synopsys VC Formal, or equivalent tools). Hands-on experience with RTL design languages such as Verilog, SystemVerilog, or VHDL. Experience with verification methodologies such as UVM (Universal Verification Methodology) or other simulation-based verification techniques. Experience with assertions (e.g., SVA - SystemVerilog More ❯
logical equivalency checking (LEC) · Verification debug support · Lint checks – RTL, CDC, RDC, DFT, UPF Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC reset control o Subsystem/SOC clock control o Subsystem/SOC More ❯
efficient and reliable RTL using Verilog. The role is hands-on and will involve extensive work within the Cadence toolchain. Key Responsibilities: Develop synthesizable Verilog RTL for core digital blocks interfacing with TMR-based analog front ends and system controllers Collaborate with the ASIC and sensor system designers to define … or related field 5+ years of experience in ASIC/FPGA RTL design, preferably for low-power wearable or biomedical applications Strong proficiency in Verilog HDL and digital design fundamentals Understanding of RTL to GDS signoff flow (STA, clock tree synthesis, DFT etc.) Hands-on experience with Cadence tools Solid More ❯
of ASIC front-end design, from specification to RTL, and with a basic understanding of RTL to tape out flow. RTL Design - VHDL or Verilog Functional verification – ideally a good knowledge of System Verilog and the use of techniques such as assertions and coverage driven verification. SoC knowledge – including the More ❯
