Senior IC Layout Engineer
- Hiring Organisation
- Intellectual Capital Resources
- Location
- Reading, Berkshire, United Kingdom
- Salary
- £ 70 K
high-speed circuits, matching constraints, minimisation of parasitics, power grids and ESD requirements Modern semiconductor process technologies including 28nm, 14/16nm, 7nm EDA tools for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop ...