Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field Solid understanding and hands-on experience with UVM and SystemVerilog Proficiency in scripting languages such as Perl, Python, or TCL Mid-Senior level As a Design Verification Engineer, the individual will spend their days collaborating More ❯
Bristol, Gloucestershire, United Kingdom Hybrid / WFH Options
Codasip
of own work YOU SHOULD HAVE: Over 5 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning More ❯
products, including microcontrollers and connectivity SoC/IP subsystem verification planning, test infrastructure development, functional verification. Test bench and test case generation using Verilog, SystemVerilog, UVM, C, Formal. Embedded C code or writing CPU-centric tests using C. Qualifications MSc in electrical engineering or equivalent or Bachelor with industrial experience More ❯
of verifying CPU architectures or other complex IP (e.g. GPUs, NNAs) Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Past verification ownership of a design block Analytical thinking, self-sufficiency and team collaboration skills Ability to work effectively across More ❯
of verifying CPU architectures or other complex IP (e.g. GPUs, NNAs) Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Past verification ownership of multiple design blocks Analytical thinking, self-sufficiency and strong team collaboration skills Ability to work effectively More ❯
bristol, south west england, United Kingdom Hybrid / WFH Options
IC Resources
and test plan, run regressions, reproduce, and debug functional and performance bugs. Proficiency with EDA tools (Candence, Mentor) and design languages including Verilog and systemVerilog Understanding of synthesis, static timing analysis, and netlist verifications UVM expertise Please note: You must have full UK working rights to be considered for this More ❯
level simulation etc ) Knowledge of verifying CPU architectures or other IP Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Analytical thinking and team collaboration skills What we'd love you to have Past verification ownership of a design block More ❯
new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system More ❯
metrics to track and report progress. Troubleshoot, debug and resolve issues while maintaining quality tracking dashboards and automated regression tests. Requirements: Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies. A solid understanding of mixed hardware/software verification approaches. Experience with RISC-V architectures More ❯
Sondrel is looking for an experienced Verification Engineers to join our global team. In this hands-on technical role, you will contribute to a variety of SoC, subsystem, and IP development projects, taking responsibility for the verification process from planning More ❯