5 of 5 Functional Programming Jobs in Cambridge

design Strong RTL design skills using Verilog, SystemVerilog, or VHDL A solid software engineering background, including experience with: Object-oriented and functional programming paradigms – C,C++,Python Compiler infrastructures, particularly domain-specific languages (DSLs) Test-driven development and writing adaptive unit tests Excellent attention to detail … areas, including: Instruction Fetch Instruction Decode Register Renaming Instruction Scheduling Vector Processing Load-Store Units Knowledge of verification methodologies, including testbench development, UVM, and functional coverage Why join? This is an opportunity to work on technology that is helping shape the future of compute. You'll collaborate with some ...

design. Strong RTL design skills using Verilog, SystemVerilog, or VHDL. A solid software engineering background, including experience with: Object-oriented and functional programming paradigms – C,C++,Python Compiler infrastructures, particularly domain-specific languages (DSLs). Test-driven development and writing adaptive unit tests. Excellent attention to detail … areas, including: Instruction Fetch Instruction Decode Register Renaming Instruction Scheduling Vector Processing Load-Store Units Knowledge of verification methodologies, including testbench development, UVM, and functional coverage. Why Join? This is an opportunity to work on technology that is helping shape the future of compute. You'll collaborate with some ...

Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL. Strong software engineering skills/background, including object‐oriented, aspect‐oriented, and particularly functional programming. Templated metaprogramming, in any language. Compiler infrastructures, particularly for domain‐specific languages. Data modeling, particularly intermediate representations for optimizing or transforming compiler passes. ...

professional experience with arithmetic RTL design or CPU RTL design in Chisel, Verilog, System Verilog or VHDL.Knowledge of at least one object-oriented or functional programming language and willingness to adopt Chisel hardware generator designAttention to detail and a focus on high-quality code and documentation.Ability to work ...

experience with arithmetic RTL design or CPU RTL design in Chisel, Verilog, System Verilog or VHDL. Knowledge of at least one object-oriented or functional programming language and willingness to adopt Chisel hardware generator design Attention to detail and a focus on high-quality code and documentation. Ability ...