6 of 6 PCIe Jobs in Cambridge

Verification (UVM/system verilog) OR Formal verification methods - Jasper Gold, C/system C Definition of complex architecture High-speed digital connectivity and protocols - Fabric, Serdes, ethernet, USB, PCIe, AMBA/AXI, CHI, MAC, PHY, cache coherency - MESI SOC/IP integration for complex embedded processors - ARM/RISC-V/CPU/GPU algorithm development/computer arithmetic More ❯

/RTL design experience in timing-critical systems. Strong background in SystemVerilog, synthesis, timing closure and verification. Hands-on with Vivado/Quartus or equivalent toolchains. Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces. Nice to Have Exposure to high-performance computing, networking or real-time data systems. Knowledge of C/C++ or Python for tooling, verification More ❯

/RTL design experience in timing-critical systems. Strong background in SystemVerilog, synthesis, timing closure and verification. Hands-on with Vivado/Quartus or equivalent toolchains. Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces. Nice to Have Exposure to high-performance computing, networking or real-time data systems. Knowledge of C/C++ or Python for tooling, verification More ❯

Digital Signal Processing (DSP) design and optimisation Excellent academic background with a degree from a top university Proficiency in SystemVerilog or VHDL Experience with high-speed external interfaces (e.g. PCIe, Aurora, Ethernet, SPI) Proven ability to take technical ownership, collaborate effectively, and deliver complex projects Position: Senior FPGA Engineer Location: Cambridge Salary: £70k£160k + equity Key Skills: FPGA, DSP More ❯

on-chip interconnects and NoCs Experience designing IP blocks (Nice to have) IP Block design for caches, coherency, memory subsystems, and interconnects Knowledge of RAS, QoS in fabrics, and PCIe/IO (a plus) Familiarity with Python Any experience with LLM accelerator chips, RISC-V processors, Cache and AMBA protocols will be advantageous. As well as working for a technologically More ❯

on-chip interconnects and NoCs Experience designing IP blocks (Nice to have) IP Block design for caches, coherency, memory subsystems, and interconnects Knowledge of RAS, QoS in fabrics, and PCIe/IO (a plus) Familiarity with Python Any experience with LLM accelerator chips, RISC-V processors, Cache and AMBA protocols will be advantageous. As well as working for a technologically More ❯