3 of 3 ASIC Jobs in Cambridgeshire

Salary: 65K - 88K GBP per annum DOE Role Overview: Work at the forefront of open silicon and hardware security, contributing to next-generation secure ASIC/SoC designs based around RISC-V, cryptographic accelerators and hardware security IP. This is a hands-on opportunity to make a direct impact … quality and timely delivery. Provide technical guidance and mentoring to less experienced engineers. Experience Required: Minimum 4+ yrs' industry experience in digital IC/ASIC design Master's degree or PhD in Electrical/Electronic Engineering or another relevant technical discipline. Strong hands-on System Verilog/RTL experience. Good ...

digital hardware and signal processing solutions is seeking a Senior Verification Engineer to join its growing engineering team in either Working within a collaborative ASIC and FPGA development environment, you will play a key role in verifying complex RTL designs, ensuring products meet functional, quality and performance requirements before deployment … development lifecycle, helping to ensure robust verification methodologies, high-quality deliverables and successful project outcomes. Key Responsibilities Develop and execute verification strategies for complex ASIC and FPGA designs. Create and maintain SystemVerilog/UVM verification environments, testbenches and coverage models. Debug RTL and verification issues, ensuring designs meet quality ...

digital hardware and signal processing solutions is seeking a Senior Verification Engineer to join its growing engineering team in either Working within a collaborative ASIC and FPGA development environment, you will play a key role in verifying complex RTL designs, ensuring products meet functional, quality and performance requirements before deployment … development lifecycle, helping to ensure robust verification methodologies, high-quality deliverables and successful project outcomes. Key Responsibilities Develop and execute verification strategies for complex ASIC and FPGA designs. Create and maintain SystemVerilog/UVM verification environments, testbenches and coverage models. Debug RTL and verification issues, ensuring designs meet quality ...