10 of 10 Synopsys Jobs in Cambridgeshire

with the project goals and needs. What you'll need to succeed Cadence: Genus, Innovus, Tempus, QRC & Conformal PnR Flow: Synthesis, LEC, CLP, Floorplan, Placement, CTS, PostCTS, Routing, STA Synopsys: Fusion compiler, Formality Synthesis, LEC Low power design techniques (power gating, DVFS etc.) Understanding in building flows and methodologies using scripting languages such as TCL, Python, Perl to support project More ❯

verification. Proficiency in RTL design techniques, including synthesis, timing closure, and verification. Experience in using UVM for functional verification of ASIC designs. Experience with EDA tools like Cadence and Synopsys for design simulation and verification. Extensive experience with FPGA emulation, design tools, and verification. Contact: For further information please contact Mícheál at Software Placements on 00353 1 or email More ❯

SoCs. Partner with cross-functional teams to enable system bring-up, debug, and feature validation on emulation platforms. Support compilation, deployment, and debug flows for emulation systems such as Synopsys ZeBu, Cadence Palladium, and Siemens Strato. Solve simulation/emulation mismatches and system-level test failures. Work closely with EDA vendors to deploy new capabilities, resolve tool issues, and influence More ❯

and advance PPA. Key Requirements: 8+ years of experience within Physical Design, ideally with exposure to low-power design techniques. Experience with Cadence (Genus, Innovus, Tempus, QRC, Conformal) and Synopsys (Fusion Compiler, Formality) tools. Understanding in building flows and methodology using scripting languages such as TCL, Python, Perl to support project development. More ❯

and methodologies to improve GPU power, performance and area (PPA). Required Skills and Experience : Experience with hardware description languages (System Verilog preferable). Experience using EDA simulators (Siemens, Synopsys, Cadence) Strong problem solving and debugging skills, and ability to closely collaborate with other teams. Experience working with version control and code review systems such as Git and Gerrit Proficiency More ❯

environment. "Nice To Have" Skills and Experience : Experience with SoC-level build and integration flows, including flow optimization and maintenance. Solid understanding of industry-standard EDA tools such as Synopsys, Cadence, and Mentor. Exposure to design databases for storing, managing, and retrieving build logs and verification results. Familiarity with data representation formats such as YAML and JSON, and markup languages More ❯

ability to closely collaborate with hardware and software teams. Good written and verbal communication skills. Experience with hardware description languages (System Verilog preferable). Experience using EDA simulators (Siemens, Synopsys, Cadence) Experience working with version control and code review systems such as Git and Gerrit Experience with scripting languages such as Python, Perl, JSON, Tcl, Make etc. Motivated, dedicated and More ❯

environment. "Nice To Have" Skills and Experience : Experience with SoC-level build and integration flows, including flow optimization and maintenance. Solid understanding of industry-standard EDA tools such as Synopsys, Cadence, and Mentor. Exposure to design databases for storing, managing, and retrieving build logs and verification results. Familiarity with data representation formats such as YAML and JSON, and markup languages More ❯

as Genus, Innovus, Tempus, QRC, and Conformal. Proficient in physical design flows including synthesis, logical equivalence checking (LEC), floorplanning, placement, clock tree synthesis (CTS), routing, and STA. Familiarity with Synopsys Fusion Compiler and Formality tools. Knowledge of low power design methodologies including power gating and dynamic voltage and frequency scaling (DVFS). Ability to develop and maintain automation scripts using … Physical Design, RTL, Place and Route (PnR), Static Timing Analysis (STA), Logical Equivalence Checking (LEC), Low Power Design, Power Gating, DVFS, Cadence Genus, Cadence Innovus, Cadence Tempus, QRC, Conformal, Synopsys Fusion Compiler, Formality, Synthesis, Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, UPF, Constraint Development, EDA Tools, Automation Scripting, TCL, Python, Perl, Semiconductor, GPU Design If you are interested in this More ❯

how often (in days) to receive an alert: Date: Jul 7, 2025 Location: Cambridge, GB, CB1 7EG Company: Ansys Requisition #: 16326 Ansys is now a part of Synopsys. Synopsys, Inc. (Nasdaq: SNPS) accelerates technology innovation from silicon to systems. Catalyzing the era of pervasive intelligence, we deliver design solutions, from electronic design automation to silicon IP, to system design … total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Ansys, part of Synopsys, we want talented people of every background to feel valued and supported to do their best work. We consider all applicants for employment without regard to race, color, religion, national … origin, gender, sexual orientation, age, military veteran status, or disability. Stay safe from recruitment fraud! We are aware of scams targeting Ansys, part of Synopsys and other companies that involve individuals posing as employees to illegitimately conduct interviews and extend false employment offers and payments to gain access to candidates' sensitive personal and financial information. All Ansys job applicants are More ❯