PhD Research Intern: Performance Modelling of 3D Stacked Memory Chiplets
Cambridge, England, United Kingdom
Hybrid / WFH Options
Hybrid / WFH Options
Chipletti
memory hierarchies, cache systems, and high-performance computing architectures. Experience with modelling and simulation tools such as Gem5, CACTI, McPAT, or equivalent. Proficiency in Python, C/C++, or SystemC for modelling and performance analysis. Strong analytical and problem-solving skills, with an ability to work independently and deliver structured outputs. Excellent written and verbal communication skills, suitable for both More ❯
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