8 of 8 Remote SystemVerilog Jobs in Cambridgeshire

verification efficiency and coverage. Required Skills and Experience: Solid understanding of SoC verification using C test cases, hardware description, and verification languages such as SystemVerilog, Verilog, or VHDL. Knowledge of computer architecture, bus protocols (e.g., AXI, AHB), and peripherals. Experience with Tcl, Python, or other scripting languages. Nice-to-Have More ❯

Job Overview: We are looking for an FPGA/Embedded-Systems Engineer to join Arm's Solution Engineering FPGA Design team on a permanent basis. The team is based in Cambridge UK, working at the forefront of Arm based embedded More ❯

in block-level verification using UVM or similar methodologies. Strong knowledge of coverage driven verification for complex designs. Proficient in specifying, creating, and debugging SystemVerilog/UVM constrained-random testbenches. Skilled in planning verification tasks and producing realistic effort and time estimates. Additional Qualities That Will Help Your Application Stand More ❯

of own work YOU SHOULD HAVE: Over 5 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning More ❯

About Us Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools More ❯

higher for Staff level - IP Level/Unit Level verification experience is a must - Experience in designing verification environments for RTL designs - Experience with SystemVerilog and UVM - Understanding of end to end verification processes - UVM knowledge is a bonus - Understanding of computer architecture, such as pipelining, memory systems etc are … offer a fantastic referral scheme which I would be happy to discuss. Keywords: Semiconductors/Verification/CPU/RTL/IP Level/SystemVerilog/C++ #semiconductors #verification #cpu #rtl #ip #systemverilog By applying to this role you understand that we may collect your personal data and store and More ❯

higher for Staff level - IP Level/Unit Level verification experience is a must - Experience in designing verification environments for RTL designs - Experience with SystemVerilog and UVM - Understanding of end to end verification processes - UVM knowledge is a bonus - Understanding of computer architecture, such as pipelining, memory systems etc are … offer a fantastic referral scheme which I would be happy to discuss. Keywords: Semiconductors/Verification/CPU/RTL/IP Level/SystemVerilog/C++ #semiconductors #verification #cpu #rtl #ip #systemverilog By applying to this role you understand that we may collect your personal data and store and More ❯

higher for Staff level - IP Level/Unit Level verification experience is a must - Experience in designing verification environments for RTL designs - Experience with SystemVerilog and UVM - Understanding of end to end verification processes - UVM knowledge is a bonus - Understanding of computer architecture, such as pipelining, memory systems etc are … offer a fantastic referral scheme which I would be happy to discuss. Keywords: Semiconductors/Verification/CPU/RTL/IP Level/SystemVerilog/C++ #semiconductors #verification #cpu #rtl #ip #systemverilog By applying to this role you understand that we may collect your personal data and store and More ❯