Senior Digital IC Design Engineer (Glasgow)
City of London, Greater London, UK
Neuranics
testbench structures Requirements: BSc/MSc/PhD in Electrical Engineering, Computer Engineering, or related field 5+ years of experience in ASIC/FPGA RTL design, preferably for low-power wearable or biomedical applications Strong proficiency in Verilog HDL and digital design fundamentals Understanding of RTL to GDS signoff More ❯
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