Principal Mixed Signal Design Verification, Team Lead
- Hiring Organisation
- Allegro Microsystems
- Location
- Musselburgh, Midlothian, United Kingdom
- Salary
- £ 70 K
teams to contribute to top-down chip architecture definitions and pre-design feasibility studies.UVM/SystemVerilog Testbench Architecture: Architect and construct robust, scalable, object-oriented SystemVerilog/UVM testbenches (including Scoreboards, Sequencers, Drivers, and Monitors) and class objects to be easily reusable by the wider global team.Requirements Traceability ...