Senior Digital Verification Engineer
- Hiring Organisation
- Allegro Microsystems
- Location
- Musselburgh, Midlothian, United Kingdom
- Salary
- £ 70 K
creating UVM-SV test environments, test plans, tests, and functional coverage.Analyzing test results, enhancing test coverage, and debugging unexpected design behavior.Running and maintaining regression test suites.Preparing and/or leading verification reviews.Collaborating with the System Engineering team on JAMA requirements.Identifying functional coverage conditions derived from microarchitecture specifications.Building mixed-signal … analog behavioral models in SystemVerilog/Verilog-AMS or electrical behavioral models in Verilog-AExperience of script generation for processing results as well as regression control configurationExperience of constrained random verification.Experience of bus-functional model development for verification of custom or industry-standard interfaces.Experience defining team deliverables and tasks ...