4 of 4 Remote/Hybrid SystemVerilog Jobs in the East of England

very generous salary on offer. This award-winning Technology company seeks a Degree qualified and commercially experienced FPGA Engineer with proven experience of SystemVerilog and RTL verification as well as having experience with Python (cocotb experience highly beneficial). In this role the successful FPGA Design Engineer will write timing ...

adjust designs to ensure timing closure - Bring value with experience in Python based verification frameworks, such as cocotb (highly advantageous) Requirements: - Strong knowledge of SystemVerilog - Experience with Python - Proven background in RTL verification - Ability to write and validate timing constraints - Understanding of low power design principles - Experience writing module specifications ...

block- and system-level designs including RISC-V cores, cryptographic IP (OTBN), and key peripherals (USB, I2C, SPI). Key Responsibilities Develop and debug SystemVerilog/UVM testbenches Create verification plans, tests, and coverage Review contributions and resolve regressions Support CI/test infrastructure Collaborate with partners through tapeout Requirements … 5+ years industry verification experience Strong SystemVerilog and UVM Full verification lifecycle experience through tapeout C and/or Python for automation Git/GitHub collaboration Desirable: Formal verification (Jasper), RISC-V/ISA knowledge, security verification, silicon bring-up, or technical leadership experience. ...

system-level designs including RISC-V cores, cryptographic IP (OTBN), and key peripherals (USB, I2C, SPI). xkybehq Key Responsibilities Develop and debug SystemVerilog/UVM testbenches Create verification plans, tests, and coverage Review contributions and resolve regressions Support CI/test infrastructure Collaborate with partners through tapeout Requirements 5+ … years industry verification experience Strong SystemVerilog and UVM Full verification lifecycle experience through tapeout C and/or Python for automation Git/GitHub collaboration Desirable: Formal verification (Jasper), RISC-V/ISA knowledge, security verification, silicon bring-up, or technical leadership experience. ...