Actel Jobs in England

4 of 4 Actel Jobs in England

Principal Firmware Engineer

Luton, Bedfordshire, England, United Kingdom
Advanced Resource Managers Limited
architecture from system requirements A structured approach to firmware design (RTCA DO-254 or similar) Experience required: FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Cryptography and anti-tamper techniques Electronics test methods and equipment HNC/HND or Undergraduate Degree (Electronic More ❯
Employment Type: Contractor
Rate: Salary negotiable
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Principal Firmware Engineer

Luton, Bedfordshire, South East, United Kingdom
Morson Talent
meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto-generated code using model driven engineering using Matlab and Simulink tools Derivation of detailed Firmware requirements More ❯
Employment Type: Contract
Rate: Hourly rate, Inside IR35
Posted:

Principal Firmware Engineer

Luton, Bedfordshire, UK
meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces s All candidates should make sure to read the following job description and information carefully before applying. Please click on the apply button to read the More ❯
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Senior / Principal FPGA Engineer

dunfermline, north east scotland, united kingdom
Certain Advantage
developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA Place and Route. Independent verification using VHDL Experience of More ❯
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